Browse Prior Art Database

Capacitance Based Net Typing for Wirability

IP.com Disclosure Number: IPCOM000109618D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 107K

Publishing Venue

IBM

Related People

LaPotin, DP: AUTHOR [+3]

Abstract

This invention is a means of distributing multi-chip module wiring more evenly across the wiring planes of a module without adversely impacting timing critical wiring. Nets that are not timing critical are chosen to be re-typed (typing is the association of a physical net with a wiring rule to model that net, based on selected criteria) to alternate wiring rules based on wirability optimization targets. The invention includes: 1. The concept of re-optimizing non-timing critical AC performance nets for wirability, based on system timing results. 2. The concept of re-optimizing real DC nets and "DC like nets" for wirability based on "DC status". 3. Improved system timing by freeing up high performance wiring planes for optimized use by critical nets. 4.

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This is the abbreviated version, containing approximately 52% of the total text.

Capacitance Based Net Typing for Wirability

       This invention is a means of distributing multi-chip
module wiring more evenly across the wiring planes of a module
without adversely impacting timing critical wiring.  Nets that are
not timing critical are chosen to be re-typed (typing is the
association of a physical net with a wiring rule to model that net,
based on selected criteria) to alternate wiring rules based on
wirability optimization targets.  The invention includes:
1.   The concept of re-optimizing non-timing critical AC performance
nets for wirability, based on system timing results.
2.   The concept of re-optimizing real DC nets and "DC like nets" for
wirability based on "DC status".
3.   Improved system timing by freeing up high performance wiring
planes for optimized use by critical nets.
4.   Improved system timing by freeing up lightly capacitively loaded
redistribution networks for use by timing critical nets.
5.   High-speed net typing algorithm capable of optimizing for
wirability by deoptimizing individual non-critical nets.

      Nets are first typed for minimum wire length.  This typing will
choose an optimized solution which will generally have a small
capacitance load limit.  This constrains many more nets to the top
wiring planes than can possibly fit.  Some of these nets are not
timing critical and could be legally wired with larger load
capacitance (e.g., deeper wiring planes) without sacrificing system
timing.  This invention provides the means for assigning rules to
non-critical nets to all...