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Browse Prior Art Database

Timing Based Net Typing for Optimized System Timing

IP.com Disclosure Number: IPCOM000109621D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 4 page(s) / 200K

Publishing Venue

IBM

Related People

Kleinman, Y: AUTHOR [+3]

Abstract

Originally, no tool was available to perform package level timing optimization on nets by altering/optimizing the net type and/or point to point connection configuration. Optimizing timing on all nets, critical and non-critical, causes needless contention for high performance I/O and wiring resources. This could render a package unbuildable, or minimally make it exceptionally difficult to wire. By only optimizing timing critical nets, the worst-case system timing paths are improved without injecting needless resource contention. This timing optimization is generally achieved without making chip changes.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 37% of the total text.

Timing Based Net Typing for Optimized System Timing

       Originally, no tool was available to perform package
level timing optimization on nets by altering/optimizing the net type
and/or point to point connection configuration. Optimizing timing on
all nets, critical and non-critical, causes needless contention for
high performance I/O and wiring resources.  This could render a
package unbuildable, or minimally make it exceptionally difficult to
wire.  By only optimizing timing critical nets, the worst-case system
timing paths are improved without injecting needless resource
contention.  This timing optimization is generally achieved without
making chip changes.

      The end result is a set of packages that are now able to
minimally meet and generally exceed system timing targets.  This
result yields an overall system performance improvement that can lead
to a more aggressive system cycle time then was originally targeted.

      Net ordering (choosing the optimal wiring rule (typing the net)
and associating the net pins with electrical pin models in the rule)
was only performed based on minimum wire length.  This was not always
optimal with regard to system timing.  Net delays and overall system
timing were not considered at all in ordering nets.  This could
impact the design team in meeting their timing objectives.

      The only way to optimize for timing was intensive pure manual
work.  A net would be ordered one way, delay would be calculated,
timing would be run, result would be analyzed.  This was a hit or
miss method where the designer would take "pot shots in the dark" in
the hope of improving timing.  This frequently led to improvement of
timing on one path at the expense of causing a timing problem on
another path.

      This invention provides an algorithmic process to generate
ordering optimized for system timing quickly and automatically.  It
also provides the fastest possible system timing to meet or exceed
stated objectives.  Finally, it performs optimized timing driven
ordering on a net by net basis that would consider all paths and
never optimize one path at the expense of creating a timing problem
on another path.

      This invention looks at all the available wiring rules that can
legally be applied to a given net.  If there are more then two pins
in the net, then the pins will be permuted into all legal positions
and analyzed in each of those positional configurations.  The
algorithm used for comparing the different rules and configurations
can by summarized by the following: "a chain is only as strong as its
weakest link".

      If we had a net with a driver and two receivers, and one
receive had a slack (the difference between the required arrival time
and the actual arrival time) of +10 ns and the second receiver had a
slack of -0.1 ns, this net will impact the system cycle time due to
the small negative slack.  The relatively large positive slack on the
other recei...