Browse Prior Art Database

Variable Delay Digital Circuit

IP.com Disclosure Number: IPCOM000109623D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 108K

Publishing Venue

IBM

Related People

Anderson, C: AUTHOR [+3]

Abstract

Disclosed are circuit techniques for implementing a variable delay function that is digitally controlled, low power, and based on a standard logic circuit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Variable Delay Digital Circuit

       Disclosed are circuit techniques for implementing a
variable delay function that is digitally controlled, low power, and
based on a standard logic circuit.

      Variable delays are useful in many communication systems.  For
example, programmable delay circuits can be valuable for data
recovery (1).  Variable capacitance delay lines (VCDLs) can be used
to reduce clock skew (2).  An all-digital circuit is often desirable
for compatibility with VLSI designs, technology, and testing.  This
article describes how a variable capacitance delay function can be
realized using a small number of modified digital inverter circuits
which are digitally controlled and operate using the logic power
supply.

      A first implementation of a variable delay circuit is shown in
Fig. 1.  The core of the circuit consists of an inverter.  One or
more capacitors C1 . . . Cn are connected to the output Y.  The other
side of each capacitor Cn is connected to the drain of an enabling
transistor En whose source is grounded and whose gate is connected to
control input Sn.  Each capacitor is effectively AC grounded and adds
to the circuit switching delay, only when its corresponding enabling
transistor is on.  The capacitors may be unitary weighted or binary
weighted in size.  The delay from input A1 to output Y is a function
of control inputs S1 . . . Sn.

      A second implementation is shown in Fig. 2.  The core of this
circuit is also an inverter.  The drains of one or more enabling
transistors E1 . . . En are connected to the inverter output Y.  A
capacitor Cn is connected between the source of each transistor En
and ground.  The internal node between each series capacitor and
enabling transistor is also connected to the drain of a smaller
transistor Dn whose source is grounded, and whose gate is the
inverter in...