Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Single Clock Module Test Provision for a Fault Tolerant Clock System

IP.com Disclosure Number: IPCOM000109630D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Salisbury, SW: AUTHOR

Abstract

Disclosed is a method for testing a single clock module in a master-slave clock system that employs triple redundancy of its master source-clock modules for fault tolerance purposes. This method bypasses a majority voting system, present in each clock module, which nominally requires the presence of two or more active input clock signals for minimum system function.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 59% of the total text.

Single Clock Module Test Provision for a Fault Tolerant Clock System

       Disclosed is a method for testing a single clock module
in a master-slave clock system that employs triple redundancy of its
master source-clock modules for fault tolerance purposes.  This
method bypasses a majority voting system, present in each clock
module, which nominally requires the presence of two or more active
input clock signals for minimum system function.

      This method applies to fault tolerant clocking systems
employing '2n + 1' redundant modules for tolerating up to 'n' fault
conditions.  In this particular n = 1, yielding a triply modular
redundant system.  All clock modules in this system are phase-locked
to one another through a combination of mutual feedback and
synchronization voting (*).  Each clock module in the system is a
phase-locked loop (PLL) with frequency steering capability provided
by a voltage-controlled crystal oscillator (VCXO).

      The synchronization voter in each clock module performs a
majority vote on the three clock signals present at its inputs.  If
two clock modules within the fault tolerant master clock source are
not present, then synchronous system operation with the remaining
clock module is excluded.  Slave receiver clocks within the system
will not have a sufficient number of clock signal inputs to pass an
output from the voter which the slave clock PLL requires for phase
locking.  The technique employed in this article emplo...