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Browse Prior Art Database

RAM Zero Array Flushing

IP.com Disclosure Number: IPCOM000109631D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 95K

Publishing Venue

IBM

Related People

Akrout, C: AUTHOR [+5]

Abstract

This article describes a valuable solution to flush a RAM array to zero within one machine cycle. Usually to implement this feature a special cell is used having an extra device. This extra device allows clearing the cell. As a result, this approach increases the cell size and is therefore unacceptable for VLSI chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

RAM Zero Array Flushing

       This article describes a valuable solution to flush a RAM
array to zero within one machine cycle.  Usually to implement this
feature a special cell is used having an extra device.  This extra
device allows clearing the cell.  As a result, this approach
increases the cell size and is therefore unacceptable for VLSI chips.

      The other way to make this feature is to write zero's in the
whole array through the bit lines.  This technique makes the power
consumption and the current peak very high; it further needs several
machine cycles to delay the current peak.  Therefore, in each cycle
only a part of the array is flushed to zero to get an acceptable
current peak and to decrease the power consumption per cycle.

      The figure illustrates the circuit block diagram and gives the
implementation of the flush zero feature in a RAM where four words
are connected on each word line requiring four additional registers.

      As apparent from the figure, the basic idea consists in the
implementation of an additional register at the side of the array.
Each bit register stores a flag bit per array word.  Instead of
flushing all the cell arrays to zero, only this register is flushed
to zero.  When the user makes a read operation, the flag invalidates
the data outputs and switches them to zero.  Afterwards, when the
word is updated in the array, the corresponding register is written
to one in order to validate the word for the next read operation.

      The physical implementation of these registers is very
important and is made carefully.  The length of the register fits
wi...