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Technique for Verifying Conditional Branch Logic

IP.com Disclosure Number: IPCOM000109633D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 121K

Publishing Venue

IBM

Related People

Adkins, RJ: AUTHOR [+2]

Abstract

A significant function to verify in processor designs with branch prediction is the case when the prediction is wrong. Conditional branches which are 'resolved wrong' cause the processor to 'back-up' in the instruction stream, and 'throw away' any results caused by the incorrect path. It is preferable to do this verification in simulation.

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Technique for Verifying Conditional Branch Logic

       A significant function to verify in processor designs
with branch prediction is the case when the prediction is wrong.
Conditional branches which are 'resolved wrong' cause the processor
to 'back-up' in the instruction stream, and 'throw away' any results
caused by the incorrect path.  It is preferable to do this
verification in simulation.

      The approach used in the simulation of the ES/9000* (820 and
900 models) was to use program-generated random streams of
instructions with lots of conditional branch instructions in the
streams.  Thousands of these testcases were generated and run in
simulation, and events in the logic were monitored to ensure the
branch paths were being resolved wrong.  While this approach found
many design problems, there were still some significant escapes to
the test floor.  The basic problem was that enough paths could not be
caused to be resolved wrong to really stress the logic.  The design
is such that a large percentage of the time the path guessed taken is
correct.  Further, when forcing 'path wrongs' by careful choice of
the conditional branch generated (and condition code value), there
was little control over the number of cycles before the path was
resolved wrong, and thus only a few instructions were executed on the
'conditional path'.

      The technique described in this article is being used on new
processor designs to achieve better verification of conditional
branch logic in simulation.  Basically a program has been written
which interfaces with the simulation model during the running of an
instruction stream, and forces a conditional path at an arbitrary
time, and then subsequently resolves the path wrong.  The way it does
this is by raising signals and setting latches to 'lie' to the logic
in the model that a conditional branch has been decoded, and later,
that the path has been resolved wrong.  The instruction stream
testcase should (eventually) complete successfully.

      Through this technique, there is complete control in simulation
over when a conditional path is started, and when it is resolved
wrong.  Many 'path wrongs' can thus be forced during a single
testcase, and many instructions can be allowed to execute on a
conditional path.  The program to do this is not trivial, since lying
to the logic causes some undesirable side effects which must be
cleaned u...