Browse Prior Art Database

Data Flow Design

IP.com Disclosure Number: IPCOM000109634D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 3 page(s) / 139K

Publishing Venue

IBM

Related People

Blachere, JM: AUTHOR [+3]

Abstract

Population rate of chips built from standard cell or gate array libraries are limited because of the random nature of those libraries. Bit-stacks are well known to be very efficient in density and delay. This article proposes a bit-stack design which is based on the existing standard cell/gate array images, then allowing to mix on a chip, random type of books, such as standard cell and gate array, with elements from the data flow library, called structured books.

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Data Flow Design

       Population rate of chips built from standard cell or gate
array libraries are limited because of the random nature of those
libraries.  Bit-stacks are well known to be very efficient in density
and delay.  This article proposes a bit-stack design which is based
on the existing standard cell/gate array images, then allowing to mix
on a chip, random type of books, such as standard cell and gate
array, with elements from the data flow library, called structured
books.

      This article describes the physical design of Data Flow
structures, known as Data Flow Stacks, Bit-Slices or Bit-Stacks.

      The main characteristics of the invention are listed as
follows:
      - It applies to any technologies such as MOS, BIPOLAR, BICMOS,
as long as the notion of standard cells or gate array exists.
      - It is assumed that metal lines run in perpendicular
directions at each level, i.e., level "1" and "3" run in the same
direction, while level "2" runs in the perpendicular direction.
      - This invention is compatible at chip image level, to existing
random logic design system, Standard Cell as well as Gate Array,
designed to be placed on a sea of gates type of image.

      It is not a custom design.

      The data flow stack is built on the same image, based on the
same cell size, referred hereafter as basic cell, of the random
logic. This technique does not require any extra rule coding at image
level.

      The orientation of the stack corresponds to the direction of
the double level of metallurgy in order to optimize the wiring
interface to/from the stack.

      It is complementary to standard cell and/or gate array to
improve chip density and performance.
      - Density advantages: the total density gain over conventional
random logic designs which depends on several factors, such as the
proportion of data flow within the chip, the size of the image, the
degree of customization of the library data flow, etc., is expected
to vary from 1.8 to 2.5 X (higher gain corresponds to larger image).
      - Delay advantages: the delay advantages will again vary with
some of the charac...