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Integratable Loss of Oscillator Circuit for Use with Standby Sparing in Conjunction with Phase Locked Loop Buffering of System Oscillator

IP.com Disclosure Number: IPCOM000109641D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 4 page(s) / 195K

Publishing Venue

IBM

Related People

Griess, KR: AUTHOR

Abstract

Disclosed is a method to detect the loss of an oscillator using the output of a PLL (Phase-Locked Loop) Frequency Synthesizer (PLLFS), which said oscillator provides the reference to, and upon detection, switch in a standby reference oscillator in a timely enough fashion as to make it transparent to the output of the PLLFS which serves as the primary system oscillator. This invention makes use of the inertial properties of a PLLFS to keep the output frequency of the PLLFS stable during the time it takes to detect the failure of the primary reference and to switch in the standby reference. By providing redundancy of the hybrid crystal oscillator, and providing a way of switching in the spare in a glitchless fashion, the availability of the system being driven is enhanced.

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Integratable Loss of Oscillator Circuit for Use with Standby Sparing in Conjunction with Phase Locked Loop Buffering of System Oscillator

       Disclosed is a method to detect the loss of an oscillator
using the output of a PLL (Phase-Locked Loop) Frequency Synthesizer
(PLLFS), which said oscillator provides the reference to, and upon
detection, switch in a standby reference oscillator in a timely
enough fashion as to make it transparent to the output of the PLLFS
which serves as the primary system oscillator.  This invention makes
use of the inertial properties of a PLLFS to keep the output
frequency of the PLLFS stable during the time it takes to detect the
failure of the primary reference and to switch in the standby
reference.  By providing redundancy of the hybrid crystal oscillator,
and providing a way of switching in the spare in a glitchless
fashion, the availability of the system being driven is enhanced.
Since the circuitry is completely integratable, the function could be
designed into existing circuitry.

      This invention is an improvement to the invention described in
(1) where the use of loss detection circuitry explained in (2) is
implied.
DESCRIPTION of INVENTION

      Fig. 1 shows a clock, Fout2, which is frequency synthesized
from a reference clock (REF_A or REF_B) by a PLLFS.  Normally, Fout2
is significantly larger than REF_A/B due to frequency multiplication
by the PLLFS.  Two PLLFSs are cascaded in this figure which may or
may not be necessary, depending on the application.  The PLLFS serves
as a "flywheel" to keep Fout2 at its desired frequency if REF_A
should become stuck fault and REF_B has to be switched in.  Two
PLLFSs provide more inertia than one.  There are 2 different sets of
"loss" circuits shown in Fig. 1.  One is for detection of loss of
REF_A at start-up, and the other is for detection of failure of REF_A
or REF_B after these clocks have been up and running for some time.
The start-up circuit is explained first.

      The start-up circuit consists of counters 1 and 4, FFs 7 and 8,
and OR gate 27.  At start-up, a Power-On-Reset (POR) clears FFs 9 and
10 causing REF_A to be used as Fref and REF_B to be de-gated.  FF 7
is reset causing a "1" to appear at the D-input of FF8.  If this "1"
is not removed before REF_B/8 goes HIGH, it will get clocked into FF
8 and cause FF 9 to de-gate REF_A and set up FF 10 to gate
REB B after REF_B's next positive edge.  If REF_A is running, REF_A/4
will be HIGH long enough to REF_B to clock it into FF 7 (thus
removing the "1") before REF_A and REF_B are running 180 degrees out
of phase when the POR is released.

      The second set of circuits uses Fout2 (or Fout1 in the case of
a single PLLFS) to continually monitor the length of the periods of
REF_A and REF_B. These circuits rely on the fact that if REF_A or
REF_B becomes stuck fault, Fout2 will remain at its initial frequency
long enough to use as a reference to measure the periods of...