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Justifiable Acknowledgement with Rapid Bit Selection

IP.com Disclosure Number: IPCOM000109642D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 7 page(s) / 382K

Publishing Venue

IBM

Related People

Christianson, MD: AUTHOR [+3]

Abstract

The design described herein is a rotational priority circuit that uses a two-stage bit search process that makes it ideal for arbitrating between large numbers of requests. A pointer to the individual bits of a multi-bit register is provided in a fair, sequential manner with a minimal amount of logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 24% of the total text.

Justifiable Acknowledgement with Rapid Bit Selection

       The design described herein is a rotational priority
circuit that uses a two-stage bit search process that makes it ideal
for arbitrating between large numbers of requests.  A pointer to the
individual bits of a multi-bit register is provided in a fair,
sequential manner with a minimal amount of logic.

      The 'Justifiable Acknowledgement with Rapid Bit Selection'
(JACKRABITS) design provides fair servicing of each and every bit
within an array of input bits, hereafter referred to as control bits.
Each time a request signal is received, JACKRABITS returns an
acknowledge signal and an encoded pointer value within no more than
three clock cycles after the request signal is initiated.  The
leftmost active bit within the sequence of control bits is the first
one indicated by the encoded pointer value.  The next request signal
results in the next leftmost active bit, to the right of the
previously indicated bit, being pointed to by the encoded value.
This 'left-to-right' process continues until all the active bits have
been serviced; once a bit has been serviced, any bits of more
significance (to the left) that subsequently become active are not
serviced until after all the remaining active bits to the right of
the one last handled are serviced.  This fairness feature prevents
bits of more significance from effectively blocking out servicing of
less significant bits.  This is essential when all the bits are
considered to have the same priority.

      JACKRABITS also uses a multiplexing feature which significantly
reduces the amount of logic which otherwise might be needed to
implement the bit selection function.  In cases where the number of
control bits is quite large (64 bits, for example), JACKRABITS
segments the control bits into groups of equal numbers of bits.  The
selection process determines which group of bits to service first and
then which bits within the chosen group to service.  The entire
procedure continues until all the control bits have been examined,
after which the process restarts.

      The JACKRABITS design consists of two logic entities aptly
named 'Justifiable Acknowledgement', or JACK, and 'Rapid Bit
Selection', or RABITS (see Fig. 1).

      JACK consists of logic designed to act as the interface between
RABITS and whatever external logic exists.  The array of control bits
to be serviced may or may not exist within JACK; in either case, JACK
minimizes logic by separating the control bits into smaller groups of
bits called 'blocks' which it multiplexes into RABITS for bit
selection.  When there are 64 control bits, for example, eight 8-bit
blocks are formed and fed into the data multiplexer.  A ninth 8-bit
bus is formed by ORing the 8 bits within each block together to
indicate when there is at least one active bit within a given block.

      When a servicing function is started, JACK gates the ninth data
path, the block...