Browse Prior Art Database

Complementary Differential Switch

IP.com Disclosure Number: IPCOM000109646D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Banker, D: AUTHOR [+3]

Abstract

The three-level differential cascode switch is highly desirable for its power performance product and its logic power. But its implementation, within the existing power supply system, has been unsuccessful until now. (Image Omitted)

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This is the abbreviated version, containing approximately 100% of the total text.

Complementary Differential Switch

       The three-level differential cascode switch is highly
desirable for its power performance product and its logic power.  But
its implementation, within the existing power supply system, has been
unsuccessful until now.

                            (Image Omitted)

      With the attainment of a vertical PNP, this complementary
differential switch (CDS) circuit attains 3 (input) levels of
differential cascoding utilizing standard power supply system.  The
upper level is selected by the input PNP transistors T11 and T12;
these serve to translate the input signal positive one Vbe to CS
transistors T7 and T8.  The middle level is selected by coupling the
input directly to CS transistors T5 and T6.  The lower level is
accessed by the input NPN transistors T3 and T4; these translate the
input negative by a Vbe to CS transistors T1 and T2.  This circuit
permits attainment of all 3 input functions in one logic circuit
depth.