Browse Prior Art Database

Wait State Cache Line Storeback

IP.com Disclosure Number: IPCOM000109668D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 4 page(s) / 215K

Publishing Venue

IBM

Related People

Funk, MR: AUTHOR [+4]

Abstract

Disclosed is a method that improves processor performance by reducing traffic to the main store system when the processor has a store-in/ write-back cache. The traffic is reduced by storing back modified/ dirty cache lines to the main store system while in wait state to reduce main store system utilization due to castouts when not in wait state. This method is most beneficial when several processor share all or part of the same main store system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 27% of the total text.

Wait State Cache Line Storeback

       Disclosed is a method that improves processor performance
by reducing traffic to the main store system when the processor has a
store-in/ write-back cache.  The traffic is reduced by storing back
modified/ dirty cache lines to the main store system while in wait
state to reduce main store system utilization due to castouts when
not in wait state.  This method is most beneficial when several
processor share all or part of the same main store system.

      One cache design option often used is a store-in or write-back
cache.  That is, if only one processor in an MP environment is
accessing the data associated with a cache line, then stores into
that cache line do not need to be sent to the main store system.  The
cache line is written to main store when it is replaced with a
different cache line if it has been modified.  These changed cache
lines are commonly referred to as "dirty."  When multiple processors
contain the data associated with the same cache line, either stores
into that cache line are passed over the main store bus to "update"
the cache line of the other processor(s) keeping the contents of the
caches coherent or an invalidate command is passed over the main
store bus upon the first store to a shared cache line to invalidate
the out of date cache line of the other processor(s).  In update
protocols shared, dirty cache lines need to be written to main store
by only one of the processors.  Let this processor be the "owner" of
the cache line.

      The times at which the contents of a cache line needs to be
written into main store are:
o    When a cache fill is required and the cache line chosen to be
filled is an owned/dirty cache line.
o    On some designs supporting a virtual addressed cache when a
translation look a side buffer miss occurs.
o    When the operating system requests that cache lines need to be
purged.

      At times when it is likely or known that the main store system
is not busy, it is beneficial to write the contents of owned/dirty
cache lines to main store system, then mark the line as unowned or
not-dirty (also called clean).  Subsequent accesses to that cache
line are still to the cache, but unless and until the line is again
changed, the contents of that cache line need not be written to main
store again.  The result and the reason for this invention is to
transfer main store system utilization from times when it is heavily
used, slowing processing down in general, to a time when it is much
less utilized.

      One time when it is very likely that the main store system is
not being used is when some of the processors are in their wait
state.  The wait state is defined as the time when there is no work
for a processor to do on behalf of the system.  So, with appropriate
controls over the hardware, better system performance can be obtained
by storing back owned/dirty cache lines while a processor is in its
wait state.

    ...