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Denormal Single Precision to Double Precision Floating Point Converter

IP.com Disclosure Number: IPCOM000109673D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Farrington, M: AUTHOR [+2]

Abstract

Converting the exponent of a single-precision (SP) denormalized number in the IEEE format to the double-precision format requires the subtraction of the number of leading zeros in the fraction (LZ) from 896 (see Fig. 1). Incrementing the ones complement of LZ to the twos complement of LZ normally requires two additional levels. Disclosed is a method which uses information from the leading zero detector to predict the carry-ins to each bit position in advance so the increment takes only one additional level.

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Denormal Single Precision to Double Precision Floating Point Converter

       Converting the exponent of a single-precision (SP)
denormalized number in the IEEE format to the double-precision format
requires the subtraction of the number of leading zeros in the
fraction (LZ) from 896 (see Fig. 1).  Incrementing the ones
complement of LZ to the twos complement of LZ normally requires two
additional levels.  Disclosed is a method which uses information from
the leading zero detector to predict the carry-ins to each bit
position in advance so the increment takes only one additional level.

      Given nLZ(1:5) is the ones complement form of the number of
leading zeros, the carry-ins to each bit position can be predicted as
follows:
o    The carry-in to bit position 11 is always one.
o    The carry-in to bit position 10 is nLZ(4).
o    The carry-in to bit position 9 is a one if and only if nLZ(4)
and nLZ(5) are ones.  This is possible only if LZ is 'XXX00'.
Therefore, a carry-in occurs for this bit position only when the
number of leading zeros is 0, 4, 8, 12, 16, or 20.
o    The carry-in to bit position 8 is a one if and only if nLZ(3:5)
are all ones.  This is possible only if LZ is 'XX000'.  Therefore, a
carry-in occurs for this bit position only when the number of leading
zeros is 0, 8, or 16.
o    The carry-in to bit position 7 is a one if and only if nLZ(2:5)
are all ones.  This is possible only if LZ is 'X0000'.  Therefore, a
carry-in occurs...