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Maintaining Status Control Register Integrity in a Multi/Asynchronous Execution Unit Processor

IP.com Disclosure Number: IPCOM000109695D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 6 page(s) / 234K

Publishing Venue

IBM

Related People

Fry, RE: AUTHOR [+3]

Abstract

Disclosed is an algorithm for maintaining a status/control register (a register that controls execution of instructions and records occurrences of architected events), in an environment which allows out of order execution of operations by the use of multiple execution units.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 32% of the total text.

Maintaining Status Control Register Integrity in a Multi/Asynchronous Execution Unit Processor

       Disclosed is an algorithm for maintaining a
status/control register (a register that controls execution of
instructions and records occurrences of architected events), in an
environment which allows out of order execution of operations by the
use of multiple execution units.

      The goal of the system designer is to achieve continuous
execution of instructions, with no hold-offs.  This requires efforts
by both the compiler and the hardware execution units.  The compiler
should schedule dependant operations so as to minimize these
hold-offs; however, the compiler cannot detect run-time hold-offs
such as data-cache misses.  The hardware must make an effort to
recognize these dependencies and to avoid them when possible.

      The status/control register, as inferred by the name, has two
functions.
1)    The first function is status recording.  As a set of
architected events occur, they are recorded in the status portion of
the register by setting a predefined flag dedicated to that event.
The status portion of the register is divided into two parts.

      The first part records the status of each event during the
entire course of the job executing (or since the status was reset).
This is referred to as the "sticky" status.  The second part of the
status register records the occurrence of the events during the
execution of the "preceding" instruction only.  This is referred to
as the "non-sticky" status.  The status/control register is then read
in order to check on the progress of the job running.
2)   The second function of the status/control register is to control
execution of instructions.  A portion of the register contains
information that the execution unit uses to control the execution of
instructions.  For example, when a floating-point overflow occurs,
the result may be infinity or the maximum number the machine can
represent (depending on the IEEE overflow trap enabled control flag).

      This invention pertains to processors with multiple execution
units.  In this environment, to maximize performance, operations may
be executed out of order.  For example, if data required for the
first operation was not available yet, but the data for the second
was, the second operation can, and should be, started first.  Note
that this assumes that either precise interrupts are not supported or
that the execution is past the interruptible pipeline stage.  In the
asynchronous processor described, a mechanism must be in place to
guarantee the integrity of the status/control register at the time of
execution of each instruction.  When the program reads the status
portion of the register, it must reflect the state of the machine at
that instant as if all instructions were executed sequentially.
Also, at the execution time of each instruction the control portion
of the register must reflect that of sequent...