Browse Prior Art Database

Read Data Sensor for Micro Channel Personal Computers

IP.com Disclosure Number: IPCOM000109713D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 4 page(s) / 124K

Publishing Venue

IBM

Related People

Klim, P: AUTHOR

Abstract

Described is an architectural implementation for personal computers equipped with a Micro Channel* (MC) to provide a method whereby asynchronous read data is acquired free of metastability so that the data can be utilized in a synchronous environment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Read Data Sensor for Micro Channel Personal Computers

       Described is an architectural implementation for personal
computers equipped with a Micro Channel* (MC) to provide a method
whereby asynchronous read data is acquired free of metastability so
that the data can be utilized in a synchronous environment.

      Typically, in an MC environment, read data may be placed on a
bus as late as 30 ns prior to the end of a command during a
default cycle or during a synchronous extended cycle.  Since read
data must be latched free of metastability so as to be handled
reliably in a synchronous environment, several factors must be
considered to establish the proper time to synchronize the data.  The
timing of each device which provides read data and the number of wait
states must be determined as well as the minimum and maximum bus
cycles.  The concept described herein provides a solution for a
synchronous extended cycle so that the data will be latched into the
clocked circuitry of each device.  The concept may directly be
applied in default cycles and may be extended to asynchronous
extended cycles.

      When minimum bus timings are assumed for the synchronous
extended cycle, read data is presented to the bus as late as 160 ns
after the -CMD active signal.  Since the MC data hold time
specification is zero ns after -CMD inactive, there is only a 30 ns
window during which read data can be expected on the data bus.
Taking into account delays at the input buffers, internal circuitry
and a possible pulse-width reduction due to the difference in
component rise and fall times, synchronization is required for
reliable operation.

      Fig. 1 shows a timing chart of a synchronous extended
input/output (I/O) read cycle with minimum timings.  To acquire read
data reliably, the -CMD signal must be double latched to avoid
metastability problems.  Fig. 2 shows the logic block circuitry used
to generate the +READ PULSE. Fig. 3 shows the circuit of the data
synchronizer which is added to provide the necessary delay for
synchronization.

      The circuit to double latch the invert of -CMD INTERNAL (-CMD
+I/O buffer and circuit delay) is accomplished by latches 1 and 2 so
that latches 3, 4 and 5 (Fig. 2) will delay t...