Browse Prior Art Database

Epitaxial Base BiCMOS Process

IP.com Disclosure Number: IPCOM000109720D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 5 page(s) / 148K

Publishing Venue

IBM

Related People

Bronner, GB: AUTHOR [+3]

Abstract

Described is a fabrication process for incorporating epitaxial base bipolar transistors in a CMOS-based BiCMOS process. The concept utilizes a non self aligned polysilicon emitter bipolar transistor, uses a low temperature epitaxy (LTE)-deposited base layer and incorporates the epitaxy base along with the emitter poly into the CMOS gate stack.

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Epitaxial Base BiCMOS Process

       Described is a fabrication process for incorporating
epitaxial base bipolar transistors in a CMOS-based BiCMOS process.
The concept utilizes a non self aligned polysilicon emitter bipolar
transistor, uses a low temperature epitaxy (LTE)-deposited base layer
and incorporates the epitaxy base along with the emitter poly into
the CMOS gate stack.

      CMOS gate polysilicon is deposited in two steps with the
epitaxial base sandwiched in between.  This allows the gate
definition to also remove the epitaxial base where it is not needed,
thereby minimizing the mask count and process complexity.  Typically,
high performance transistors require base widths less than 1000 Ao.
LTE achieves narrow bases and by incorporating germanium in the
epitaxy base, bandgap engineering.  The bipolar device will have
improved performance.

      The concept described herein provides a process that allows the
integration of epitaxial base bipolar transistors into a CMOS process
with a minimum of extra masking steps.  The process consists of three
basic steps: a) a non-self-aligned bipolar emitter; b) LTE for the
bipolar transistor base for high performance.  This allows the
fabrication of thin bases and/or bases incorporating Si/Ge alloys,
and c) incorporates a LTE base and emitter poly stack into the CMOS
gate poly for process simplicity.

      Essentially, the process merges a single NPN transistor with a
high performance CMOS process.  Four extra masks are required to form
the subcollector, reachthrough, base, and emitter.  An epitaxial base
is incorporated without extra masks, as compared to a more
conventional implanted base transistor.  The fabrication processing
steps are as follows:
      1)  A p1-/p1+ wafer is used as the substrate.
      2)  N1+ subcollectors are formed.  One possible method to
accomplish the forming would be as follows:
           - Grow oxide thermally - 200 nm.
           - Pattern and etch the oxide with the subcollector mask.
           - Implant the arsenic subcollector and drive it in.
           - Strip the oxide.
           - Grow LTE cap to prevent autodoping.
           - Grow 1.0 mm of p1- epi.
      3)  Isolation and N wells are formed.  One process sequence
could use thermal oxide (ROX) for isolation, or shallow trench
isolation could also be used.
           - Form nitride/oxide stack.
           - Pattern and etch the stack with the ROX mask.
           - Apply a mask which opens the ROX area only where
n-channels are built.
           - Implant the field stop boron.
           - Strip the resist.
           - Apply the n well mask and n well dopant.
           - Strip the resist.
           - Grow isolation oxide thermally.
      4)  The reachthrough region is formed to contact the
subcollector.
 ...