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Conductive Etch Stop for Self Alignment Bipolar Transistors

IP.com Disclosure Number: IPCOM000109722D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 4 page(s) / 180K

Publishing Venue

IBM

Related People

Comfort, JH: AUTHOR [+2]

Abstract

Described is a method that allows fabrication of self-aligned SiGe epitaxial (epi) base bipolar transistors without detrimental oxidation of the SiGe in the active device region.

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This is the abbreviated version, containing approximately 41% of the total text.

Conductive Etch Stop for Self Alignment Bipolar Transistors

       Described is a method that allows fabrication of
self-aligned SiGe epitaxial (epi) base bipolar transistors without
detrimental oxidation of the SiGe in the active device region.

      Generally, one of the difficulties associated with the
fabrication of heterojunction bipolar transistors using SiGe is the
need to avoid oxidation of the SiGe layer in the intrinsic device
region.  A high number of surface states induced by Ge pile-up during
oxidation of the SiGe films may preclude proper junction isolation
and could lead to unacceptably high base currents.  In epitaxial base
transistor processes it is often preferred to use semi-rox isolation
to define the emitter opening using a nitride stack and selective
oxidation.  In this case, a disposable oxide spacer is used to align
the extrinsic base implants with respect to the emitter opening.
This provides both a high performance vertical profile through the
use of epi deposition and a high performance lateral profile through
self-alignment and control of the extrinsic base resistance.
However, since SiGe is present in the intrinsic base region, semi-rox
isolation can lead to oxidation of the SiGe in the vicinity of the
emitter opening.

      The concept described herein is designed to overcome the above
difficulties and involves the realization that a wet chemical
etchant, which removes intrinsic Si without etching heavily doped
p-type Si, may be used to remove the Si buffer in the emitter opening
provided a heavily doped wet chemical etch stop, such as a p++ epi
layer, is positioned immediately above the SiGe device region.  The
concept provides a means whereby semi-rox isolation is used for
lateral self- alignment in an epi base SiGe transistor without
oxidizing the intrinsic base region.  A p++ conductive etch stop is
used to isolate the SiGe containing the intrinsic base region from an
undoped Si oxidation buffer layer, and KOH is used to selectively
remove the buffer from the emitter opening prior to emitter
formation.

      Figs. 1 to 8 show the fabrication flow for the emitter
definition and extrinsic base self-alignment process.  The following
outlines the steps required in the process:
      -    Epi base deposition (Fig. 1) consists of:  a) Arbitrary
SiGe base profile in n or p type; b) Thin (@100 o), heavily doped
(p++@>2E20 B/cm3), conductive etch stop layer; c) Intrinsic Si buffer
region for consumption during semi-rox isolation (@300-400 o).
      -    Oxide/Nitride deposition and patterning for the emitter
opening stack.
      -    Option A (Fig. 2): Implant before oxidation - Sidewall
formation and removal for extrinsic base ion-implantation; 700 o low
temperature oxidation, e.g., HIPOX, for semi-rox isolation; Link
implant defined by the nitride stack, if desired (Fig. 4).
      -    Option B (Fig. 3): Implant after oxidation - 700 o low
temperature oxida...