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High Speed External Interrupt Handler for Real Time System

IP.com Disclosure Number: IPCOM000109726D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 4 page(s) / 172K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+2]

Abstract

One of the main objectives for a real time embedded microprocessor is to react very quickly to an external interrupt. But the interrupt handling has also to be flexible enough to support a wide range of applications; a fine trade-off between hardware and software solutions needs to be reached. For this purpose a new scheme of interrupt handling is proposed which complies with the IBM RISC System/6000* (RS/6000) architecture. This proposal is flexible as it permits to change interrupt priority by software, keeping interrupt detection in hardware, resulting in a higher density.

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High Speed External Interrupt Handler for Real Time System

       One of the main objectives for a real time embedded
microprocessor is to react very quickly to an external interrupt.
But the interrupt handling has also to be flexible enough to support
a wide range of applications; a fine trade-off between hardware and
software solutions needs to be reached.  For this purpose a new
scheme of interrupt handling is proposed which complies with the IBM
RISC System/6000* (RS/6000) architecture.  This proposal is flexible
as it permits to change interrupt priority by software, keeping
interrupt detection in hardware, resulting in a higher density.

      The first level of interrupt handler is done by hardware logic,
as illustrated by the figure.  The new proposal defines three
different architected areas located in the system memory:

      Vector table: Each entry of this 64-bit double-word table
memorizes the state to load in the processor when the associated
interrupt has to be serviced.

      Mask table: Each entry of this 64-bit double-word table
memorizes the new value to copy into the EIM register, when the
associated interrupt has been taken in account.

      Old context frame stack: Ressources of the interrupted task are
saved in this part of the system memory before handling the new
process.  As with a conventional stack, it grows from lower addresses
to higher ones.

      Besides IBM RS/6000 architected interrupt registers (such as
EIS, EIM, SRR0-1 and MSR), additional hardware resources have been
defined: NVAR, CVAR and CSPL registers

      (EIS) External Interrupt Summary: When an interrupt is
requested by an external source, the EIS bit mapped to that source is
set to one.  This EIS bit remains set by the external source until
reset by software.  The 64-bit EIS register always accepts an
interrupt request from an external source regardless of the state of
the associated EIM bit.

      (EIM) External Interrupt Mask: The 64-bit EIM register provides
the programmer with a mechanism to selectively inhibit or enable any
external interrupt request.  Setting any bit of the EIM to one
enables the interrupt request (associated EIS bit).  EIS and EIM
registers are logically ANDed to determine if the current task may be
interrupted.

      (SRR0-1) Save/Restore Registers: SRR0 memorizes the 32-bit
address of the instruction of the interrupted process that would have
executed next.  SRR1 is loaded by the SPL (System Priority Level) of
the interrupted task as well as the 16 lower bits of the MSR.

      (MSR) Machine State Register: The 16 lower bits of this 32-bit
register defines the modal state of the processor.  The External
Interrupt Enable bit (EE) when set, enables external interrupt
handling by the processor.

      (NVAR) New Vector Address Register: This 6-bit register
memorizes the higher encoded number of the interrupts currently
available.  A leading zero operation perfor...