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Input Skewing Testing: A New Test Dimension and Application to a High Speed Bipolar RAM

IP.com Disclosure Number: IPCOM000109728D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Hivert, C: AUTHOR [+2]

Abstract

Disclosed below is a test concept that has shown to be efficient in increasing the test coverage factor of a High Speed Bipolar RAM (HSBRAM). The method consists in introducing the possibility of a timing skew between chip input signals. In a specific case, bit address skew has led to a new test, which has significantly reduced the defect rate at system level, without impacting chip final test yields. Input skewing has shown to be the primary test dimension in catching 'defect-induced disturbs' at system level.

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Input Skewing Testing: A New Test Dimension and Application to a High Speed Bipolar RAM

       Disclosed below is a test concept that has shown to be
efficient in increasing the test coverage factor of a High Speed
Bipolar RAM (HSBRAM).  The method consists in introducing the
possibility of a timing skew between chip input signals.  In a
specific case, bit address skew has led to a new test, which has
significantly reduced the defect rate at system level, without
impacting chip final test yields.  Input skewing has shown to be the
primary test dimension in catching 'defect-induced disturbs' at
system level.

      Decreasing the defect level of product chips delivered to
system's assembly lines is increasingly important, specially for
high-end systems, which have to combine complexity and high
reliability.  Chip final test is of key importance in that
perspective, and has to minimize the escape level, to ensure proper
system reliability but also minimize assembly costs with respect to a
high speed bipolar static RAM used in high performance computers as a
cache memory, trying to solve a test escape problem (a specific
random defect affecting internal circuits).  An original test
concept, described below, has been introduced and shown to be very
effective, while other test parameters (temperature, power supplies,
cycle time, patterns) have been shown to be second-order ones.

      Until now, digital chip final testing was performed with input
signals (bits) of the same nature (Addresses, Data Ins, Controls)
totally synchronized (act...