Browse Prior Art Database

Multiple-cache Chip ROS Access using Self Identifying Logic

IP.com Disclosure Number: IPCOM000109732D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Countryman, GJ: AUTHOR [+3]

Abstract

Increasing demands on cache memory size require multiple-cache memory chips. By incrementally adding cache memory modules the cache size can be increased. Furthermore, a common practice in getting data into the cache chips from read-only storage (ROS) is via a common dotted (byte-wide) data bus with a storage control unit (SCU) controlling the data movement using load strobes. However, as cache chips are added, the number of control signals increases proportionally with the number of cache chips. This invention eliminates the need for unique control lines from the SCU by putting self-identifying logic in the cache chips.

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Multiple-cache Chip ROS Access using Self Identifying Logic

       Increasing demands on cache memory size require
multiple-cache memory chips.  By incrementally adding cache memory
modules the cache size can be increased.  Furthermore, a common
practice in getting data into the cache chips from read-only storage
(ROS) is via a common dotted (byte-wide) data bus with a storage
control unit (SCU) controlling the data movement using load strobes.
However, as cache chips are added, the number of control signals
increases proportionally with the number of cache chips.  This
invention eliminates the need for unique control lines from the SCU
by putting self-identifying logic in the cache chips.

      For purpose of illustration four data cache chips have been
chosen.  Each chip is dotted onto a ROS byte-wide data bus;
therefore, a word of data will require four separate ROS transfers.

                            (Image Omitted)

      The first byte of a data word transmitted goes to the first
data cache chip, the second transfer to the second chip, the third
transfer to the third, and the fourth to the fourth.  One method of
handling this transfer is to have the SCU send a separate control
signal to each cache chip to indicate when to accept data from the
ROS data bus.  Note that this requires four control signals in a
four-cache chip system.

      The four control signals sent by the SCU can be reduced to one
by implementing a counter and the following logic in the data cache
chips.  Each of the cache chips presently has a unique id which is
set by using resistors tied up or down on the planar.  This id can be
used to initialize...