Browse Prior Art Database

Process for a High Performance Bipolar Based BiCMOS

IP.com Disclosure Number: IPCOM000109775D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 3 page(s) / 132K

Publishing Venue

IBM

Related People

Sun, YC: AUTHOR [+2]

Abstract

Disclosed is a process for fabrication of complementary BiCMOS circuits, based on a high-performance, double-polysilicon, self-aligned bipolar device structure. The use of chem-mech polish allows the bipolar base polysilicon to serve as a completely self-aligned diffusion source and contact for the CMOS source-drains.

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Process for a High Performance Bipolar Based BiCMOS

       Disclosed is a process for fabrication of complementary
BiCMOS circuits, based on a high-performance, double-polysilicon,
self-aligned bipolar device structure.  The use of chem-mech polish
allows the bipolar base polysilicon to serve as a completely
self-aligned diffusion source and contact for the CMOS source-drains.

      The process relies on a novel use of chem-mech polish to
minimize the device topography, and to self-align the source-drains
with the gates (or vice-versa).  In one embodiment (which hereafter
will be referred to as the "separate CMOS/bipolar approach"), the
CMOS devices are formed separately, before the bipolar devices are
defined.  The base poly in the bipolar process then provides the
dopant for the source and drain as well as providing contacts.  The
excess poly de posited over the CMOS gates is removed via a chem-mech
polish step, so that the source-drains are self-aligned to the gates.
In the other embodiment (hereafter to be referred to as the "the
parallel CMOS/bipolar approach"), the CMOS devices are defined in
parallel with the bipolar devices, with the emitter opening etch also
defining the CMOS gate regions, and the bipolar sidewall also being
used for the CMOS sidewall.  A chem-mech polish step of the emitter
(and gate) poly then allows self-alignment of the gate poly to the
source/drains.  In more detail, the two processes are described
below.
The separate CMOS/bipolar approach

      Most of the CMOS device processing occurs after the device
isolation is finished, and before the bipolar device processing.  A
planar recessed field oxide isolation (STI) is assumed.  After
implanting and annealing the reach-throughs (for the bipolar
devices), n-wells, p-wells and threshold adjustments (CMOS), the CMOS
gate oxide is grown, followed by a polysilicon deposition and ion
implantation(s) for the gate.  The polysilicon can be silicided at
this stage (polycide), and a cap dielectric deposited for protection
of the gate during subsequent processing.  The gates are defined
lithographically, etching away the excess polysilicon on the field.
A sidewall is formed, the remaining gate oxide over the source-drain
and bipolar device regions is etched away, and the base polysilicon
for the bipolar devices is deposited.  Oxide is grown or deposited
and the poly is doped appropriately for PMOS, NMOS source-drains, and
npn or pnp extrinsic bases.  A short chem-mech poli...