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Pitch Minimization Compaction Algorithm for the Macro-remap

IP.com Disclosure Number: IPCOM000109797D
Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-24
Document File: 4 page(s) / 129K

Publishing Venue

IBM

Related People

Lee, JF: AUTHOR [+2]

Abstract

A software program is disclosed that solves the macro-remap problem with a pitch-minimization compaction algorithm.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Pitch Minimization Compaction Algorithm for the Macro-remap

       A software program is disclosed that solves the
macro-remap problem with a pitch-minimization compaction algorithm.

      A layout compactor (1) is a CAD tool which converts loose IC
layouts into tight ground-rule clean layouts.  This approach is
applicable to the following remap problem: We already had the design
of an IC chip manufactured in an old technology, and would like to
map it into a new technology with minimum amount of effort.  Because
fabrication geometries generally shrink in the new technology,  the
old chip layout is no longer compact.  Theoretically, the old chip
layout can be remapped into the new technology with a full-chip
compaction.  However, as of today, the compaction of the whole VLSI
chip is impossible because of the huge memory and CPU time required.
A divide and conquer method is then needed to break this chip-remap
problem into manageable pieces, i.e., the remap of macros and
inter-macro global wiring (see Figure 1 for an example).  One
approach is to map each macro into the new technology with a "free"
compaction, and then reconnect the global wires.  This reconnection
task can be as time consuming as a complete redesign, since pins of
macros will be in quite different positions after a free compaction.
For "pitch-designs" which require all global wires and macro
positions to fall on certain wiring grid, the following alternative
approach of macro remap is more attractive.

      In a pitch design, sizes of macros and positions of global
wires are on the grid defined by pitch sizes, say, dx, dy.  For
example, in the x-direction, the left and right boundaries of macro
i, x positions of j-th pins of macro i, and x positions of i-th
global wires, denoted respectively by

                            (Image Omitted)

                                                    (1)
In a new technology with smaller ground rules, we may be able to use
a smaller pitch size while keeping the pitch numbers, ni, npij, nwi,
unchanged.  Therefore, we need to solve a "constrained" compaction
problem for each macro in which the pitch numbers are kept unchanged.
Then inter-macro wiring can be achieved simply by shrinking the
original global wires linearly with pitch size.

      More precisely, the "pitch" compaction problem can be
formulated as follows: Given an initial macro layout and a set of
pitch numbers, ni, npij, nwi, find the smallest pitch dx, dy such
that both ground rules and pitch constraints are satisfied.  Let us
consider "pitch" compaction in...