Browse Prior Art Database

Multibus Synchronization for Raid-3 Data Distribution

IP.com Disclosure Number: IPCOM000109964D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Bronson, TC: AUTHOR [+4]

Abstract

Disclosed is a method for utilizing a synchronized multibus data distribution within a Direct Access Storage Device (DASD) Array Controller implementing a RAID architecture. A DASD array controller requires high-speed communication on a block basis between two types of modules known as a striper control (SC) chip and a device control chip (DC). The SC chip receives or sends data across a high-speed IPI-3 connection and distributes the data to one, two, three or four DC chips depending on the system configuration. Each DC chip receives or sends this data across a slower IPI-2 connection. The SC may stripe (interleave) data to/from the DCs requiring them to operate in concert, or the SC may operate with one DC at a time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multibus Synchronization for Raid-3 Data Distribution

       Disclosed is a method for utilizing a synchronized
multibus data distribution within a Direct Access Storage Device
(DASD) Array Controller implementing a RAID architecture.  A DASD
array controller requires high-speed communication on a block basis
between two types of modules known as a striper control (SC) chip and
a device control chip (DC).  The SC chip receives or sends data
across a high-speed IPI-3 connection and distributes the data to one,
two, three or four DC chips depending on the system configuration.
Each DC chip receives or sends this data across a slower IPI-2
connection.  The SC may stripe (interleave) data to/from the DCs
requiring them to operate in concert, or the SC may operate with one
DC at a time.  In the case of data rebuild (reading data stream(s)
and one parity stream to re construct and rewrite an erroneous
portion of the composite data stream) it is necessary for the SC to
read from some DCs while simultaneously writing to one DC.

      Within this DASD Array Controller, there is a requirement for a
bus with the following characteristics:
1.   High-speed data transfer on a block basis.
2.   Interconnection of one master to one of four slaves.
3.   A method of synchronizing simultaneous transfers with multiple
slaves for striping (interleaving) operations.
4.   Separate controls for each slave to allow for independent
operation and multiple configurations.
5.   Minimal risk with regard to timing variations resulting from
chip process variations (in order to maintain high data integrity).
6.   Minimal chip-to-chip interconnections due to technology
constraints.

      The SBUS is an acronym for Synchronous Bus.  It is designed
with two-phase level-sensitive clocking in mind.  A cycle is defined
as the time from t...