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Browse Prior Art Database

Test Circuit for Serial Data Lines

IP.com Disclosure Number: IPCOM000109965D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Koehler, T: AUTHOR [+2]

Abstract

This article describes a test circuit which reliably detects failures of the serial data flow.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 69% of the total text.

Test Circuit for Serial Data Lines

       This article describes a test circuit which reliably
detects failures of the serial data flow.

      During the transmission of data across bit-serial interfaces,
it is frequently necessary to detect when a particular data line
fails as a result of interruptions or short-circuits.  In contrast to
bit-parallel transmission methods, there is no additional test line
(parity bit) that may be used for this purpose.

      The line protocol does not permit the introduction of a
redundancy check or a longitudinal redundancy check LRC in the data
flow either, which merely detects intermittent errors but no complete
line failures.

      A reliable method of detecting and signalling serial data flow
failures is to look for state changes in the signal at the point of
receipt.  Thus, the edges of the serial data flow are used for
testing.

      The absence of such edges is evaluated by a circuit which
generates an error signal for further processing.  The error signal
must be triggered both by a statistical "0" signal and a statistical
"1" signal on the data line in order to allow the detection of
short-circuits to ground and those following a positive supply
voltage, as well as interruptions during which the open receiver
input drifts to random levels.

      A single shot is triggered by any arbitrary edge, positive and
negative, of the signal received.  The metastable time of this single
shot until it resumes...