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High Performance Error Correction Code Implementation for Microprocessors

IP.com Disclosure Number: IPCOM000109967D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Eng, RC: AUTHOR [+3]

Abstract

Described is a high-performance error correction code (ECC) implementation for microprocessors equipped with dynamic random-access memory (DRAM). The implementation is an improvement over parity checking devices and other ECC mechanisms in that not only are single-bit memory errors detected but are corrected without sacrificing performance, unless an error is detected.

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This is the abbreviated version, containing approximately 56% of the total text.

High Performance Error Correction Code Implementation for Microprocessors

       Described is a high-performance error correction code
(ECC) implementation for microprocessors equipped with dynamic
random-access memory (DRAM).  The implementation is an improvement
over parity checking devices and other ECC mechanisms in that not
only are single-bit memory errors detected but are corrected without
sacrificing performance, unless an error is detected.

      Parity checking of DRAM is typically implemented to ensure
reliable memory operation.  In parity checking implementations, a
single-bit error is considered a non-recoverable DRAM error.  To
provide ECC capability enhances the recoverability from a single-bit
error, but generally reduces the high-speed performance of the
microprocessor.  The concept described herein improves on the ECC
implementation by providing an implementation that detects and
corrects all single-bit errors, but does not degrade system
performance by employing a correct-only-on-error mechanism.

      Typically, the ECC memory implementation using DRAM requires
the addition of wait states (WSs) to the microprocessor cycle for
accessing the data from memory, plus additional WSs for the ECC
mechanism to process and possibly correct the data from memory.
Given the fact that: (1) the vast majority of memory read accesses do
not result in an error, and, (2) the ECC mechanism can detect an
error faster than it can correct an error, significa...