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Emitter Cap for Self Aligned Emitter Base Isolation in Low Topography Epitaxial Transistors

IP.com Disclosure Number: IPCOM000109981D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 102K

Publishing Venue

IBM

Related People

Comfort, JH: AUTHOR [+2]

Abstract

Described is a fabrication method utilizing an emitter cap for self-aligned emitter-base isolation in low topography epitaxial (epi) transistors. The process allows for the integration into BiCMOS process flows by incorporating single-poly-like bipolar technology. The process utilizes an emitter cap layer to allow oxidative consumption during isolation.

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Emitter Cap for Self Aligned Emitter Base Isolation in Low Topography Epitaxial Transistors

       Described is a fabrication method utilizing an emitter
cap for self-aligned emitter-base isolation in low topography
epitaxial (epi) transistors.  The process allows for the integration
into BiCMOS process flows by incorporating single-poly-like bipolar
technology.  The process utilizes an emitter cap layer to allow
oxidative consumption during isolation.

      Typically, epi base processing for heterojuction (SiGe) base
devices is concerned with the prevention of SiGe oxidation near the
emitter base junction during the isolation process.  Oxidation
consumes the intrinsic base material and may lead to poor isolation
in the case of a SiGe base device.  To overcome these concerns, the
concept described herein provides a method of implementing a thin,
blanket emitter cap layer after intrinsic base deposition and before
defining the nitride for the emitter opening.  The cap layer is then
consumed during local oxidation as opposed to the intrinsic base,
thereby avoiding oxidation of SiGe in the base.  Once the nitride
stack is removed, contact can be made with the remaining emitter plug
using a second polysilicon layer and may proceed to define the
junction through conventional implantation and annealing.  A
polysilicon cap may also reduce lateral oxidation and suppress
oxidation enhanced by serving as a sink for injected interstitials.

      The use of an emitter cap prior to junction isolation actually
provides for three alternative emitter formation methods.  In this
embodiment, an emitter contact is made with a second polysilicon
layer and must contend with two poly interfaces during diffused
emitter junction formation.  If an oxide layer is placed between the
emitter cap and the intrinsic base, then the emitter plug can...