Browse Prior Art Database

Floating Point Carry Out of the Rounder

IP.com Disclosure Number: IPCOM000109987D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Chu, TV: AUTHOR [+4]

Abstract

This invention avoids renormalization when a carry out of the rounder occurs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Floating Point Carry Out of the Rounder

       This invention avoids renormalization when a carry out of
the rounder occurs.

      The final stage of the floating point is to round the
intermediate mantissa in parallel and subtracting the normalization
amount from the intermediate exponent.  These two operations produce
the final mantissa and final exponent at nearly the same time.  One
exception to this is if there is a carry out of the rounder (see
below).
                                1.111 . . . 111   intermediate
exponent
                             +               1   round up
                              10.000 . . . 000

      To get the final answer, you must renormalize the mantissa
(shift one bit to the right) and add one to the exponent.  The figure
shows the writeback cycle for the floating point.  Above the dashed
line is the writeback cycle prior to the Cout (carry out of the
rounder) problem.  The diagram below the dashed line details one
possible solution to this problem.  The cost of this solution, in
additional space consumed by the two OTS macros would be
approximately 5 ns extra delay in the exponent data flow and 3 ns
extra delay in the mantissa data flow.  With the severe size
constraints and an aggressive cycle time for the floating point, an
alternative solution was necessary.

      A number of observations lead to this solution.  First, the low
probability of a 'Cout' occurring.  Assuming a normalized mantissa,
we expect a 50% probability of each bit, except the MSB, of being a
'1'.  It is also reasonable to assume a 50% chance of rounding the
intermediate mantissa up (i.e., add one).

      For IEEE double precision, which is normal operating mode,
expect a carry out of rounder to occur less than once every 2**53
instructions.  A Cout can only occur if all bits in the mantissa are
'1'.  The 52 fraction bits and rounding up all needing to be '...