Browse Prior Art Database

Single Hot Reset Replaces Two Signals

IP.com Disclosure Number: IPCOM000109989D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Klim, P: AUTHOR

Abstract

A single circuit is used to generate two hot reset signals that were previously generated by two separate circuits. In personal computer systems based on Intel microprocessors, hot reset signal is issued by one of two sources -- "Port 92H" or a Keyboard Mouse Controller (KMC) unit -- to switch the microprocessor from virtual to real mode. By presently integrating these functions into a single circuit, system circuitry is reduced and organization of the KMC function is simplified.

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Single Hot Reset Replaces Two Signals

       A single circuit is used to generate two hot reset
signals that were previously generated by two separate circuits.  In
personal computer systems based on Intel microprocessors, hot reset
signal is issued by one of two sources -- "Port 92H" or a Keyboard
Mouse Controller (KMC) unit -- to switch the microprocessor from
virtual to real mode.  By presently integrating these functions into
a single circuit, system circuitry is reduced and organization of the
KMC function is simplified.

      A hot reset request is issued by the operating system to switch
the system state from virtual to real mode.  The request is delayed
by 6.7-13.4 microseconds, to allow the processor to complete internal
housekeeping before it receives the reset signal, and is generated by
one of two different methods.  In one method, specific data is
written to Port 92H (Bit 0 = 1), and in the other method, a command
"FE" is written to the port (64H) associated with the KMC.

      By using the single circuit shown in the illustration, a single
pulse delay network 1 is shared for both methods.  Delay network 1 is
activatable by AND circuit 2 and OR circuit 3, when an appropriate
bit is set in either register 4 (Port 92 Hot Reset Register) by a
Port 92H (I/O) Write operation or register 5 by a command FE signal.
If the reset is activated by a Port 92 Write, register 4 must be
cleared before another reset sequence can be activated through the
same...