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Efficient ESA/370 Read Channel Programming

IP.com Disclosure Number: IPCOM000109998D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 9 page(s) / 414K

Publishing Venue

IBM

Related People

Hrelic, D: AUTHOR [+4]

Abstract

The hardware capability of ESA/370* I/O Architecture has the potential of achieving very good bandwidth. Experience has, however, shown that system performance (and consequently the I/O performance as well) degrades significantly during heavy I/O loads. One of the major reasons for this is inefficient use of the hardware architecture both in terms of Channel programming and I/O driver software. Latency, which is primarily caused by software path lengths, is the major contributor to this inefficiency. Additionally, poor buffer management techniques and Channel programming cause adverse effects on the ESA/370 system as a whole. For example, numerous I/O interrupts are disruptive to ESA/ 370 pipelined execution which consequently degrades the entire system performance.

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Efficient ESA/370 Read Channel Programming

       The hardware capability of ESA/370* I/O Architecture has
the potential of achieving very good bandwidth.  Experience has,
however, shown that system performance (and consequently the I/O
performance as well) degrades significantly during heavy I/O loads.
One of the major reasons for this is inefficient use of the hardware
architecture both in terms of Channel programming and I/O driver
software.  Latency, which is primarily caused by software path
lengths, is the major contributor to this inefficiency.
Additionally, poor buffer management techniques and Channel
programming cause adverse effects on the ESA/370 system as a whole.
For example, numerous I/O interrupts are disruptive to ESA/ 370
pipelined execution which consequently degrades the entire system
performance.

      Classically, computer systems use buffering to read ahead and
blocking to reduce the number of I/O initiations.  The buffering
ahead is important because it allows overlap of CPU processing and
the transfer of data.  In addition the buffering ahead can smooth out
temporary imbalances in the processing rates of the I/O and the CPU.
The benefit of reading ahead does not come without cost.  When the
read ahead operation completes, an interrupt is presented that causes
suspension of the processing of earlier data.  If the I/O operation
did not reach successful completion, then error correction is
initiated.  The interrupt also allows the buffer management to record
the fact that the block has been read.  During this interruption a
further read ahead operation is usually scheduled.  All of these
activities delay the current processing.

      In some applications blocking can be used to reduce the number
of interrupts.  This is done by initiating I/O for a number of blocks
and presenting a single interrupt when the last block is read.  This
technique is most effective when the process is severely I/O limited.
In the I/O limited case long blocks accumulate naturally.  However,
if the I/O and CPU capacity are well balanced then blocks do not
form.  When a server is ready to process data, but all of the current
block has not been read, the server may go idle brvause it does not
know how much of the current block has been successfully read.

      This offers an algorithm that is optimal with respect to
interrupts associated with buffering ahead.   The only time that
interrupts will happen is at times that the server is idle or when
further read ahead is impossible because all of the buffers have been
used.  Thus, there are no interrupts of a running server.

      We introduce a new ESA/370 Channel programming algorithm for
receiving data into ESA/370 systems that is both path length
conscious and limits incoming I/O interrupts to the absolute bare
minimum.  The basic idea is to keep the Channel running at 100
percent utilization and present an interrupt to ESA/370 applications
only when abso...