Browse Prior Art Database

Single Inline Memory Module Stuck at Fault Error Injector

IP.com Disclosure Number: IPCOM000110008D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 131K

Publishing Venue

IBM

Related People

Lee, VH: AUTHOR

Abstract

Disclosed is a single inline memory module (SIMM) address/data stuck-at fault error injector that can be used to simulate error condition for testing memory power-on self-test (POST) codes.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Single Inline Memory Module Stuck at Fault Error Injector

       Disclosed is a single inline memory module (SIMM)
address/data stuck-at fault error injector that can be used to
simulate error condition for testing memory power-on self-test (POST)
codes.

      Modern personal computers and workstations use SIMMs to
implement system memory (main memory).  These machines also have
memory POSTs which are executed after the machines are powered up.
To fully test these POST codes, both normal conditions and error
conditions handling should be verified throughout POST code's
unit-testing.  In this aspect of testing, error conditions require an
error injecting tool to force memory errors during the execution of
the POSTs.  The general design concept of this stuck-at fault error
injector is also applicable to systems which may not use SIMMs for
their main memory.

      Fig. 1 shows the block diagram of this fault injector.  Row
Adr/Msk registers, Col Adr/Msk registers, and Injected Data register
are set up through the parallel port.  The Row Adr/Msk registers
store the row address bits (AR0-AR9) and the row address mask bits
(MR0-MR9) of the memory location(s) at which stuck-at fault is
injected.  The Col Adr/Msk registers store the column address bits
(AC0-AC9) and column address mask bits (MC0-MC9) of that same memory
location(s).  When a mask bit is set, the corresponding address bit
is ignored.  This allows ranges of addresses subjected to the fault
injecting, if desired.

      Latches F and latches B capture the row address during a memory
access.  If the SIMM is single-sided, then latches B can be omitted.
These latches have an active-low latch-control input and an active
low output-enable input.  These inputs of two latches are connected
to RASF and RASB, respectively.  Since only one RAS signal, RASF or
RASB, becomes active during an access, data outputs of the two
latches are connected together to form the RW0-RW9 inputs of the
comparator logic block.  The common data inputs of these latches also
serve as the CO0-CO9 inputs of the comparator logic block.

      Fig. 2 shows the block diagram of the comparator logic block.
The XOR COMPARATOR has an active-low enable control input and an
active-low output.  If the enable control input is HIGH, the output
of the comparator is HIGH.  Comparison of two input signal groups
takes place only when the enable control input is LOW, then the
output represents the comparison result.

      The two output signals of the comparator logic block, HIT and
MISS, are used to control the output enable inputs of the two 3-state
drivers.  Stuck-at faults are only injected during memory read
accesses.  During memory write accesses, written data are presented
to the SIMM unchanged.

      Manual setup is required to configure the injector as...