Browse Prior Art Database

Improving the Performance of a Cache that Uses a Page Searching Technique with the Addition of an Invalidate/Castout Address Translation Buffer

IP.com Disclosure Number: IPCOM000110024D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 92K

Publishing Venue

IBM

Related People

Grohoski, GF: AUTHOR [+3]

Abstract

This invention improves upon the performance of a cache that uses the Page Searching methodology described in US Patent 5,077,826 to determine if a desired line of data from a given page exists in the cache. The Page Searching methodology applies to a virtually addressed cache where each entry in the cache's directory contains both the real addresses of the page in main storage from which the data came and the most significant bits of the virtual address. The cache's performance is improved by placing the entries for the lines from the same page of main storage in a predetermined sequence that permits the lines to be searched for by page. Therefore, if the desired line is not found, it is possible that another line from the same page already exists in the cache.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Improving the Performance of a Cache that Uses a Page Searching Technique with the Addition of an Invalidate/Castout Address Translation Buffer

       This invention improves upon the performance of a cache
that uses the Page Searching methodology described in US Patent
5,077,826 to determine if a desired line of data from a given page
exists in the cache.  The Page Searching methodology applies to a
virtually addressed cache where each entry in the cache's directory
contains both the real addresses of the page in main storage from
which the data came and the most significant bits of the virtual
address.  The cache's performance is improved by placing the entries
for the lines from the same page of main storage in a predetermined
sequence that permits the lines to be searched for by page.
Therefore, if the desired line is not found, it is possible that
another line from the same page already exists in the cache.  If this
occurs, then the real address for the secondary line will be used to
construct the address for the primary line, thus eliminating an
address translation operation.  The desired data can then be fetched
directly from main storage.

      Thus the directory acts as a translation look-aside buffer
(TLB) without incurring the hardware cost associated with actually
implementing a TLB.

      This invention proposes using a buffer called the Invalidate/
Castout Address Translation (ICAT) buffer.  The ICAT buffer would
hold translated page addresses that would no longer exist in the
cache directory.  The translated addresses would be placed in the
ICAT buffer when the last line of data from a given page of main
storage had to be invalidated or cast out of the cache in order to
make room for a new line of data in the cache.  Thus the ICAT buffer
would contain only the most recently translated page addresses that
are no longer present in the cache directory.  The cache directory
would contain translated page addresses of currently active lines in
the cache.  This increase in the range of translated addresses held
in the cache would reduce the number of cache "misses" requiring an
address translation.  The result of this would be an improvement in
cache performance.
Fetch Operati...