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High Performance Edge Triggered D Latch Designed Directly from Circuit Components, Rather than Using Several Levels of Logic Gates

IP.com Disclosure Number: IPCOM000110026D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+4]

Abstract

An edge-triggered D latch is a common logic element, generally composed of several levels of logic gates, as shown in Fig. 1. The function of the latch is to hold its output constant and respond to the input (IN) only when a specific clock edge occurs at node CLK. Fig. 2 shows an input, clock, and output waveform for a rising edge-triggered D latch.

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High Performance Edge Triggered D Latch Designed Directly from Circuit Components, Rather than Using Several Levels of Logic Gates

       An edge-triggered D latch is a common logic element,
generally composed of several levels of logic gates, as shown in Fig.
1.  The function of the latch is to hold its output constant and
respond to the input (IN) only when a specific clock edge occurs at
node CLK.  Fig. 2 shows an input, clock, and output waveform for a
rising edge-triggered D latch.

      The circuit of Fig. 3 is disclosed here as a high performance D
latch using a minimal amount of real estate.  The transistors and
resistors in Fig. 3, taken as a group, replace the several levels of
logic shown in Fig. 1.  Typically, each of the gates shown in Fig. 1
would be made up of several transistors and resistors.  Therefore,
the real estate saving is obvious.  Significant power savings can
also be realized over the latch in Fig. 1

      An additional feature of this new D latch is improved
performance.  Since the levels of logic have been eliminated,
clock-to-output delays are extremely fast.  Instead of having data
pass through several logic gates, the rising edge of the clock is
translated directly into an output signal, significantly reducing
clock-to-output delays.

      The operation of the disclosed latch can be broken up into two
stages.  Stage 1 consists of T1 through T5 and R1 through R5.  Stage
2 consists of T6 through T9 and R6 through R11.  Each stage has both
a transparent mode to allow data to pass through and a latched mode
to hold data, depending on the phase of the clock.  Each stage is
also designed to be in the opposite mode of its counterpart.
Therefore, when Stage 1 is transparent, Stage 2 is latched, and vice
versa.  T3, T4, and T5 of Stage 1 are responsible for holding the
actual data furing its latch mode, while T2 prohibits the input from
changing the latched data.  Similarly, T8 and T9 of Stage 2 hold the
data in this stage, while T7 blocks any new input.  In the
transparent modes, T2 and T7 allow data to pass into the respective
stage of the latch.

      When node CLK is low, Stage 1 is transparent, allowing data to
pass from node IN to node 1 though T1.  R4 sets an up level unless
current is drawn through T1 by the input signal.  T3 and T4 are off.
Stage 2 is in latched mode with T6 held off by T7.  T8 and T9
are holding previously latched data.

      When node CLK rises, Stage 2 goes into transparent mode,
allowing T6 to pass data from node 1 to node OUT.  T9 is off.  At
the same time, T1 is turned off by T2, and T7 and T8 hold the
data that had been present at node 1 in Stage 1...