Browse Prior Art Database

Selective SOI and Integration with Planar Oxide Isolated Bulk Devices

IP.com Disclosure Number: IPCOM000110027D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Davari, B: AUTHOR [+3]

Abstract

Disclosed in this article is a method to fabricate thin Silicon-On-Insulator (SOI) and bulk MOSFET devices on the same wafer. The process can be integrated to form planar oxide isolation regions in the bulk device area.

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Selective SOI and Integration with Planar Oxide Isolated Bulk Devices

       Disclosed in this article is a method to fabricate thin
Silicon-On-Insulator (SOI) and bulk MOSFET devices on the same wafer.
The process can be integrated to form planar oxide isolation regions
in the bulk device area.

      Thin, fully-depleted SOI MOSFET devices are known to have
significant speed and soft-error advantage over bulk devices.
However, due to material problems, thin SOI CMOS by Lateral Epitaxial
Over-growth (ELO) and Chemical-Mechanical Polish (CMP) methods
usually have higher defect density, and the active area widths are
limited to 10 um or less (1).  These problems can be alleviated if
only a small number of SOI devices are fabricated on a VLSI chip.
The SOI devices are placed in the critical paths, as well as
sensitive nodes in the memory cell, to improve the chip speed and
reduce soft-error rate.

      There are several ways to fabricate selective SOI devices among
conventional bulk devices.  One of them is described in Fig. 1 (a)-
(d).  First, a blanket oxide is grown on a silicon wafer followed by
depositing an etch-stop layer, as shown in (a).  Lithogaphic steps
are then applied to etch polish stop and oxide regions, as shown in
(b).  Here, the right side represents bulk device area where large
oxide openings are created.  The left side represent the thin SOI
device area where only small oxide openings are etched to form the
seed areas.  One then grows...