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Chem-mech Polish for Self Aligned Emitter Base Isolation in Single Poly Epi-base Transistors

IP.com Disclosure Number: IPCOM000110032D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 97K

Publishing Venue

IBM

Related People

Comfort, JH: AUTHOR [+3]

Abstract

Disclosed is a method for self-aligned emitter/base isolation in single poly epitaxial base bipolar transistors with minimal oxidation and annealing. This process is ideally suited for the fabrication of either homojunction (Si) or heterojunction (SiGe) epitaxial base bipolar transistors.

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Chem-mech Polish for Self Aligned Emitter Base Isolation in Single Poly Epi-base Transistors

       Disclosed is a method for self-aligned emitter/base
isolation in single poly epitaxial base bipolar transistors with
minimal oxidation and annealing.  This process is ideally suited for
the fabrication of either homojunction (Si) or heterojunction (SiGe)
epitaxial base bipolar transistors.

      This invention considers the extension of an emitter/base self-
alignment scheme developed for implanted base bipolar devices (1) to
epitaxial base devices, and in particular to SiGe base devices.  When
fabricating SiGe base devices, one must avoid oxidation of SiGe in
the active device or junction isolation regions.  Otherwise, Ge will
pile up at the oxide/silicon interface during oxidation (2) and lead
to poorly passivated junctions and abnormally high base currents.

      In this invention, oxidation of the SiGe region is avoided by
using a deposited oxide in conjunction with a thin thermal oxide to
isolate the emitter/base junction defined by a nitride/oxide stack.
A thin oxide cap is grown on a pure silicon buffer layer deposited
above the SiGe base region.  A thin nitride layer is then deposited
and patterned to define the emitter opening.  Finally, a high quality
oxide is deposited over and around the nitride pedestal.  A Chemical-
Mechanical (Chem-Mech) Polish planarization scheme is then used to
remove the deposited oxide from the top of the nitride pedestal.
After planarization, the nitride is selectively removed prior to
polysilicon emitter contact formation.  Since the emitter opening is
still defined by a nitride pedestal, a sidewall scheme may still be
used to space extrinsic base implants away from the emitter contact
in a self-aligned manner [1].  The ability to use a deposited oxide
for EB isolation reduces the overall thermal cycle associated with
the process and facilita...