Browse Prior Art Database

Method to Control the Geometry and Vertical Profile of Via Holes in Substrate Materials

IP.com Disclosure Number: IPCOM000110033D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 6 page(s) / 191K

Publishing Venue

IBM

Related People

Bassous, E: AUTHOR [+2]

Abstract

The method described herein illustrates three-dimensional replication which extends silicon-patterning capabilities to packaging structures and overcomes the resolution limitations of machining methods such as drilling and punching.

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Method to Control the Geometry and Vertical Profile of Via Holes in Substrate Materials

       The method described herein illustrates three-dimensional
replication which extends silicon-patterning capabilities to
packaging structures and overcomes the resolution limitations of
machining methods such as drilling and punching.

      Via holes in single and multilayer packaging structures for
interconnecting integrated circuit (IC) chips are generally formed by
mechanical drilling and punching techniques.  Due to the limited
resolution capabilities of these techniques, high-density via-hole
array patterns with small diameter vias and high aspect-ratio cannot
be readily generated.  Inadequate control of vertical profiles also
imposes limitations on the ability to tailor and personalize via hole
geometry.

      This method suggests improved fabrication methods which
overcome these limitations and provide greater flexibility in the
design of via hole patterns.  Applications include via, pin-grid and
wiring patterns in ceramic, glass, plastic, and composite materials
for products such as metallized ceramic (MC), multichip module (MCM),
multilayer ceramic (MLC), and card/board interconnections.  The
fabrication methods are described below.

      The 3-dimensional (3-D) patterning capabilities of silicon are
superior to punching and drilling techniques and can be extended to
packaging materials by 1:1 contact replication methods such as
molding, embossing, and casting. High-resolution via-hole patterns
etched in silicon wafers could thus be replicated in moldable
materials to generate features with minimum horizontal dimensions of
approximately 5 micrometers, and aspect ratios in the range of 1:3.
By taking advantage of the etching characteristics, IC
microfabrication techniques and crystal structure of silicon,
excellent control of the size, shape and density of vias is achieved.
Furthermore, unique and predictable 3-D configurations can be
generated which provide flexibility in the design and fabrication of
circuit wiring.

      Fig. 1 illustrates the basic approach.  The desired circuit and
via-hole pattern is defined and etched in a single-crystal silicon
wafer by standard IC processing methods.  A mirror-image replica of
this pattern is then formed in a durable material by coating, casting
or molding methods.  This replica now serves as a reusable mold to
emboss or stamp the original circuit pattern into a moldable
substrate.  Employing a mirror-image replica, instead of the original
silicon wafer, is useful in applications where ruggedness of the mold
and dimensional tolerances are important considerations.  For
example, the geometry of cavities and trenches etched in silicon are
usually better defined and controlled than 'convex' relief features
such as rails and studs.

      Fig. 2 illustrates how pyramidal-shaped vias can be formed by
anisotropic etching of a silicon wafer of (100) orientation.  The
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