Browse Prior Art Database

32-Bit (ECC) Partial Write Data Conversion with a Cache Memory System

IP.com Disclosure Number: IPCOM000110038D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 6 page(s) / 192K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+4]

Abstract

This article describes a method for use in a computer system to solve the partial write performance penalty by converting partial memory write cycles to full memory write cycles if the addresed memory location is in the cache memory subsystem. This assumes that ECC is generated on a 32-bit word.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

32-Bit (ECC) Partial Write Data Conversion with a Cache Memory System

       This article describes a method for use in a computer
system to solve the partial write performance penalty by converting
partial memory write cycles to full memory write cycles if the
addresed memory location is in the cache memory subsystem.  This
assumes that ECC is generated on a 32-bit word.

      The popular operating systems of today, DOS and OS/2*, and most
applications are based on 16-bit data widths.  This is a
compatibility statement with the less powerful Intel 80286-based
systems.  The fact that the operating systems and applications are
based on 16-bit data leads to the majority of the memory write cycles
being a partial 32-bit write.  The performance impact of partial
memory write cycles is substantial.

      An error correcting code (ECC) memory interface generates
additional information called syndrome bits that are stored with the
actual write data.  These syndrome bits are used to correct the data
on memory reads should a memory error occur.  If the memory write
cycle is a partial write, the ECC memory interface must first read
the addressed memory location.  With the read memory data, the ECC
memory interface will combine the unwritten portion of the addressed
memory location with the partial memory write data to form a full
32-bit data transfer.  The syndrome bits are then regenerated for the
full 32-bit data and written to memory with the data.  If the
original memory write cycle was a full 32-bit data width, the read
and modify portions of the write cycle would have been avoided.

      The solution disclosed herein is to convert the partial memory
writes to full memory write before they are transferred to the ECC
memory interface.  Most high performance Intel 80486 systems have
second level memory cache systems.  Performance analysis has shown
that the majority of memory writes the 80486 executes will reside in
the second-level cache memory.  The cache memory of a 80486 system
will always contain full 32-bit data.  During the early stages of a
memory write cycle, the cache memory system checks to see if the data
is in the cache memory and whether or not the current cycle is a
partial write.  If both conditions are true, the cache system will
convert the current cycle to a full 32-bit memory write.

      There are a number of variations on the implementation of the
partial write conversion cycles.  The first is simply connecting the
80486 CPU, cache memory system and the memory interface on a single
bus.  Fig. 1 shows a high-level block diagram of this type of bus
structure.  Fig. 2 shows the timing diagram associated with Fig. 1.

      During CLK 1, the 80486 starts a new memory write cycle.
During CLK 2, the cache subsystem decodes whether or not the current
cycle is a partial write by observing the 80486's BE's and W/R
signals.  The decode is illustrated by the PARTIAL WRITE DECODE
signal.  In...