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Planarized Metallized Field Effect Transistor

IP.com Disclosure Number: IPCOM000110054D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 115K

Publishing Venue

IBM

Related People

Bronner, G: AUTHOR [+4]

Abstract

A technique is described whereby a field-effect transistor (FET) structure and fabrication process provides the ability to convert source-drain epi and gate poly-silicon to tungsten in one step, thereby lowering the sheet resistance. Minimal differential height between source and drain is produced.

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Planarized Metallized Field Effect Transistor

       A technique is described whereby a field-effect
transistor (FET) structure and fabrication process provides the
ability to convert source-drain epi and gate poly-silicon to tungsten
in one step, thereby lowering the sheet resistance.  Minimal
differential height between source and drain is produced.

      Tungsten typically plays an important part in VLSI technology.
It continues to be explored for source-drain and gate metallization,
contact metallurgy and via filling as a second level metal.
Selective tungsten deposition is typically achieved by means of
hydrogen reduction and the use of silicon reduction to grow the
desired tungsten thickness is not generally known.  The hydrogen
reduction method results in severe encroachment and junction leakage.
In addition, the selectivity in depositing tungsten produced by the
hydrogen reduction method strictly depends on the pre-deposition
condition of the wafer and the design of the chamber.

      To overcome the drawbacks of the hydrogen reduction method, the
concept described herein provides a combination of a process which
grows selective epi-silicon on source and drain, and converts exposed
silicon to tungsten.

      A standard FET structure is shown in Fig. 1.  The new FET
structure disclosed herein is shown in Fig. 2.  Selective epi is used
to raise the source and then tungsten is used to metallize the
source/ drain and gate.  By blocking the gate with the oxide cap,
selective epi is deposited at 875oC on the already implanted source
and drain.  The oxide cap is removed from the g...