Browse Prior Art Database

Very Tight Coupling for Multiple Conventional Processors

IP.com Disclosure Number: IPCOM000110064D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Coleman, R: AUTHOR [+3]

Abstract

Disclosed is a very tight coupling scheme for multiple conventional processors. It is well known that certain problems do not lend themselves to loose coupling. If the communication latency is excessive on such a problem, the task at hand is better run n a single processor even if multiple processors are available. See (*). An example of such a problem is the use of multiple processors to simulate a single more complex processor, where conventional processors must act to complete a single complex instruction. The advantage of using conventional processors is reduced design time (possibly using macros), and flexibility in changing architectures, resulting in common part numbers.

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Very Tight Coupling for Multiple Conventional Processors

       Disclosed is a very tight coupling scheme for multiple
conventional processors.  It is well known that certain problems do
not lend themselves to loose coupling.  If the communication latency
is excessive on such a problem, the task at hand is better run n a
single processor even if multiple processors are available.  See (*).
An example of such a problem is the use of multiple processors to
simulate a single more complex processor, where conventional
processors must act to complete a single complex instruction.  The
advantage of using conventional processors is reduced design time
(possibly using macros), and flexibility in changing architectures,
resulting in common part numbers.  In order to compete in performance
with a true implementation of such an architecture, the communication
and handshaking latency needed between processors must be much less
than the instruction execution latency.  Tight coupling is also
goodness in pure sense, in that a processor capable of Very Tight
Coupling is also capable of any looser coupling required.

      Several processors are assumed to exist on one chip.  In
addition, the registers of any processor are assumed accessible to
any other (e.g., a single large register space), as described in
previously available art.
New Art:
1.   The condition code registers of all processors are made
addressable to each other.
2.   Each processor can be stopped via a hold signal.
3.   The system of conventional processors is augmented with a
sy...