Browse Prior Art Database

Fabrication of a Borderless Local Interconnect for Advanced BiCMOS

IP.com Disclosure Number: IPCOM000110070D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 112K

Publishing Venue

IBM

Related People

Gambino, J: AUTHOR [+4]

Abstract

Disclosed is a process which forms borderless local interconnect for wiring contacts in advanced BiCMOS devices. To reduce cell area and improve density, this local wiring must be formed in a manner which allows the interconnect to partially overlap the contact area. For bipolar applications, it must also provide high conductivity to meet circuit speed requirements.

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This is the abbreviated version, containing approximately 52% of the total text.

Fabrication of a Borderless Local Interconnect for Advanced BiCMOS

       Disclosed is a process which forms borderless local
interconnect for wiring contacts in advanced BiCMOS devices.  To
reduce cell area and improve density, this local wiring must be
formed in a manner which allows the interconnect to partially overlap
the contact area.  For bipolar applications, it must also provide
high conductivity to meet circuit speed requirements.

      Although Al is widely used as a low resistivity conductor, it
is undesirable at the device level because of penetration problems
associated with Si intermixing (1).  Other refractory metals such as
W exhibit the necessary conductive and refractory properties
(electromigration resistance) which make it suitable for local
interconnect, but the inability to pattern this material selectively
to silicided diffusions using RIE has precluded its use.  An etch
stop is required to completely remove rails of metal left over
topography since anisotropic etching requires large amounts of
overetch.  This etch stop must exhibit selectivities of greater than
10:1 for a viable process.

      As a specific example, the use of metal as a contact to
diffusion in a CMOS device is cited for this process.  This
application places stringent requirements on the metallization
because borderless contacts are needed to minimize transistor cell
size.  The starting point for this invention is a CMOS transistor
which has been formed in a self-aligned manner and has exposed
silicided diffusion regions 10 as seen in Fig. 1.  The following
process module is utilized to form a borderless local interconnect
(Fig. 2):

      Process Module
      1.  deposit Ti layer 20
      2.  oxidize Ti to form TiO2 30
      3.  deposit Si 40 and W 50 metallization
      4.  pattern Si, W bilayer with conventional lithography
      5.  form silicide 60 (Fig. 3)
      6.  deposit Ti layer 70
      7.  etch Ti layer 70

      The W and Si are patterned with standard lithography and RIE,
stopping on the TiO2 layer 30, as shown in Fig. 2. A TiO2 etch stop
is selected for this process because it exhibits much greater
resistance to etch than SiO2 in F-based RIE.  This enhanced
selectivity is supported by the relative volatility of TiF4 from TiO2
which is much low...