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Browse Prior Art Database

Global and Local Device Control Mechanism with Arbitration Bus

IP.com Disclosure Number: IPCOM000110087D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Fukuda, M: AUTHOR [+4]

Abstract

This article describes a new device control mechanism for multiprocessors. This invention enables any system devices, such as I/Os and memories, to be mapped as a local or a global device to a memory space. It utilizes an arbitration mechanism, which is indispensable for a multiprocessor to implement flexible mapping between processors and devices.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Global and Local Device Control Mechanism with Arbitration Bus

       This article describes a new device control mechanism for
multiprocessors.  This invention enables any system devices, such as
I/Os and memories, to be mapped as a local or a global device to a
memory space.  It utilizes an arbitration mechanism, which is
indispensable for a multiprocessor to implement flexible mapping
between processors and devices.

      Conventional multiprocessors have devices that are mapped as
local devices completely dedicated to an individual processor or as
global devices shared by all processors.  However, they have the
following disadvantages: (1) A local device can be accessed only by
the processor that is directly connected to it.  The other processors
do not have any physical path to access it.  (2) Global devices are
shared by all processors, and therefore each of them must be mapped
to a different address space.  (3) Local and global devices are
strictly defined, and they cannot be exchanged at any time.  This
invention solves these disadvantages and provides a flexible mapping
scheme between processors and devices.

      This invention has a device controller that is placed between a
device and a system bus, as shown in Fig. 1.  The device controller
consists of an arbitration selector and an address decoder, as shown
in Fig. 2.  The arbitration selector is connected to the arbitration
bus to see if it should accept the processor access.  Each processor
has a unique arbitration code to avoid the bus contention.
Therefore, the arbitration selector can identify which processor is
making an access by seeing...