Browse Prior Art Database

State Machine Programmable Logic Devices

IP.com Disclosure Number: IPCOM000110089D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 92K

Publishing Venue

IBM

Related People

Suffern, ES: AUTHOR

Abstract

Disclosed is a method for adding programmable state machine to an Erasable Programmable Logic Device (EPLD). The addition of the programmable state machine, with its associated Arithmetic Logic Unit (ALU) and local registers for storing information, allows the logic to perform complex addition, subtraction, comparison, and shifting functions not available on today's EPLDs.

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State Machine Programmable Logic Devices

       Disclosed is a method for adding programmable state
machine to an Erasable Programmable Logic Device (EPLD).  The
addition of the programmable state machine, with its associated
Arithmetic Logic Unit (ALU) and local registers for storing
information, allows the logic to perform complex addition,
subtraction, comparison, and shifting functions not available on
today's EPLDs.

      Manufacturers offer EPLDs with various sizes of available
programmable logic space to allow designers the ability to design
logic in a short period of time.  The EPLDs are also available with
different logic clock cycles to match varied performance objectives.
The EPLDs capture a number of standard transistor-transistor logic
(TTL) devices, reduce the redundant function, and then wire the
equivalent TTL logic.

      Logic sequencers are specialized EPLDs used to sequentially
perform a series of operations based on the inputs to the chip.
Logic sequencer EPLDs limit the number of states and the amount of
function they can perform.  Also, as with EPLD, the ability to wire
the chip once the function has been designed can present problems if
the manufacturer's wiring program is not sophisticated.

      The key to the design of the programmable state machine in an
EPLD is an embedded macro containing an ALU, local storage registers,
and an EEPROM.  Fig. 1 shows the finite state machine macro.  A 4096-
by-16 bit EEPROM, ALU, local store, and input/output multiplexers are
common to all desi...