Browse Prior Art Database

Method for Card Hot Plug Detection and Control

IP.com Disclosure Number: IPCOM000110100D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 149K

Publishing Venue

IBM

Related People

Oman, PW: AUTHOR [+2]

Abstract

Disclosed is a method for controlling system bus signal disruptions that may occur as a result of card "hot plugging."

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

Method for Card Hot Plug Detection and Control

       Disclosed is a method for controlling system bus signal
disruptions that may occur as a result of card "hot plugging."

      The system in which this disclosure is to be used contains "hot
plug" support facilities, which consist of multi-level pin lengths to
control the sequencing of power and signal connections while a card
is being inserted into or removed from the system.  In-rush current
is controlled by a current limiter provided by the bulk power supply,
such that instantaneous current drain on the card will not surpass a
specific limit.  Normally, the sequencing of power and bus pins is
such that a card is:  a) powered-on and stable prior to bus pins
making contact on insertion; and b) powered-off after bus pins break
contact on removal.  A signal pre-charge network on each system bus
signal conditions the signal prior to its pin making contact during
insertion.  A service bus is available on the backplane and is
connected to all system bus-attached cards as well as to the bulk
power supply.

      The connector system used for the adapter cards consists of
four levels of pins.  The longer two levels are used for power and
power control sequencing, while the two shorter levels are available
for system bus and service bus connections (see Fig. 1).

      The mechanism disclosed contains the following facilities (see
Fig. 2):
      1.   A set of shortest pins, which will "make" last and "break"
first when inserting or extracting a card, respectively; these pins
contain a service bus interface, which is connected to all adapter
cards, the system card, and bulk power supply.
      2.   A longest pin, which will "make" first and "break" last
when inserting or extracting a card, respectively; this pin contains
a "card enable" signal, and there is one of these signals connected
between each adapter card and the system card.
      3.   Control logic for the service bus which is contained on
the system card and which, via the service bus controls, input
signals or senses the state of output signals contained on the
adapter cards or within the bulk power supply.

      When a card is inserted into a backplane slot, a current
limiting scheme built into the bulk power supply limits the in-rush
of bulk supply current via a "power enable" signal at the second
longest level of connector pins (after bulk power and bulk power
return, which are at the longest level).  The bulk power-on and
current limiting mechanism is automatically invoked in the bulk
supply when the "power enable" pin in the adapter makes contact with
the backplane.  At this time, all the adapter's system bus
transceivers are in the disabled or high-impedance state.  When the
shortest pin of the adapter makes contact with the backplane, the bus
transceivers can be enabled under the control of the service bus
logic via the adapter's "card enable" signal.

      The "card enabl...