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Algorithm to Calculate Data Used by Logic Synthesis of Timing Critical Designs

IP.com Disclosure Number: IPCOM000110108D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 112K

Publishing Venue

IBM

Related People

Chan, HH: AUTHOR [+4]

Abstract

This invention improves the efficiency of the ASIC (Application Specific Integrated Circuit) design process by providing the synthesis program with data which results in quicker convergence on a satisfactory solution (timing wise) and possibly a better solution (cell count wise). The formulas used in deriving this data will be discussed later. First, for background information, a short description of the IBM synthesis process will be discussed.

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Algorithm to Calculate Data Used by Logic Synthesis of Timing Critical Designs

       This invention improves the efficiency of the ASIC
(Application Specific Integrated Circuit) design process by providing
the synthesis program with data which results in quicker convergence
on a satisfactory solution (timing wise) and possibly a better
solution (cell count wise).  The formulas used in deriving this data
will be discussed later.  First, for background information, a short
description of the IBM synthesis process will be discussed.

      IBM synthesis programs go through at least two synthesis
passes.  The first pass optimizes for cell count and is a relatively
quick job.  The second pass is a much longer job since it utilizes a
calculation-intensive static timing analyzer to improve logic paths
with excessive delay.  Often correcting one path introduces excessive
delay in other paths.  The designer has to hand synthesize some paths
when synthesis does not find solutions in a reasonable amount of
time, then go through another synthesis pass.

      It should be obvious that if the first synthesis pass did a
poor job, then much computer time and designer's time could be wasted
in subsequent passes.  These subsequent synthesis passes focus on
improving one path at a time, resulting in increased cell counts
(since breaks up large efficient books into multiple smaller books
that are easier to "parallel up" to reduce fanout) and increased
delays in many paths not focused.  This article will elaborate on how
to calculate the minimum capacitive loading level (i.e., capacitance
due to fanout) at which the technology book's power level should be
stepped up.

      Recently, an algorithm was programmed to automatically
calculate the capacitive loading level at which to bump a technology
book power level.  It is based on the delay data tables provided by
two ASIC foundries.  The LSI LCA200K and Toshiba TC160G ASIC
libraries were successfully processed by this program.

      This algorithm analyzes the delay equations of two adjacent
power books.  For example, in a CMOS technology the time delay of a
technology book is a function of load capacitance which includes pin
capacitance and wire segment capacitance.  Therefore, a simple linear
relationship can be expressed by the following equation:
TimeDelay(Capacitance) = K4 * Capacitance + K5
K4 and K5 are coefficients of the delay equation.  They can be
extracted from the delay tables provided by the ASIC foundry.  The
intersection, XP in the graph below, of the two delay equations is
the capacitance load value a...