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Technique for Power Management in Signal Processors

IP.com Disclosure Number: IPCOM000110116D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 116K

Publishing Venue

IBM

Related People

Carmon, D: AUTHOR [+3]

Abstract

This is a technique for power management in digital signal processor (DSP) subsystems. DSP subsystems are used for the implementation of a wide variety of functions, covering such areas as speech, music, modems, and video. The high-performance requirements of DSP systems generally equate to short processor cycle times, fast memory access rates, and relatively high clock rates; factors that contribute to high power consumption. While power conservation is important in DSP subsystems in general, it is becoming particularly important as these subsystems are being designed for use in portable or laptop computers.

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Technique for Power Management in Signal Processors

       This is a technique for power management in digital
signal processor (DSP) subsystems.  DSP subsystems are used for the
implementation of a wide variety of functions, covering such areas as
speech, music, modems, and video.  The high-performance requirements
of DSP systems generally equate to short processor cycle times, fast
memory access rates, and relatively high clock rates; factors that
contribute to high power consumption.  While power conservation is
important in DSP subsystems in general, it is becoming particularly
important as these subsystems are being designed for use in portable
or laptop computers.

      Power management is based on the power characteristics of CMOS
technology.  Specifically, it is based on the observation that, for a
given voltage level, power is dissipated mostly by circuits changing
states.  Little power is dissipated when circuits are held in fixed
states, as is the case when the circuits are not activated by a
clock.  Theoretically, non-clocked power can be made virtually zero
by careful                 ference design.  The difference between
clocked and non-clocked power can be used to advantage in a DSP
subsystem by having a means of deactivating the clocks to most of the
circuits once useful processing has been completed.  In this manner,
power dissipation is approximately proportional to processor loading.

      Fig. 1 is a block diagram for power management using dynamic
clock control.  It is important to note that no changes are required
in the data flow or instruction set of the digital signal processor
(DSP) that is the core of the subsystem.  The implementation of the
processor requires that the clock signals be major elements of the
architecture to be separated from the interrupt handler so that they
may be separately controlled.  All necessary circuits for clock
control are added to the periphery of the processor core.  A 'sleep
pattern register' or halt register is attached to the common data bus
of the DSP and is addressed...