Browse Prior Art Database

Bus Arbitration Method for a Two Way Multiprocessor

IP.com Disclosure Number: IPCOM000110121D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 4 page(s) / 96K

Publishing Venue

IBM

Related People

Nakada, T: AUTHOR [+2]

Abstract

This article describes a new arbitration method for a two-way multiprocessor system. This arbitration method has the following advantages over conventional ones: (1) it reduces the arbitration overhead when one of the two processors continuously uses the processor shared bus, and (2) it guarantees fairness so as not to starve one of the processors. Multiprocessor systems that use a common processor bus should have an arbitration mechanism to avoid bus contention. In conventional arbitration methods, a processor should always perform arbitration before starting to use the processor bus. Using this invention, however, the arbitration overhead can be reduced while keeping the bus use fair to both the processors.

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Bus Arbitration Method for a Two Way Multiprocessor

       This article describes a new arbitration method for a
two-way multiprocessor system.  This arbitration method has the
following advantages over conventional ones: (1) it reduces the
arbitration overhead when one of the two processors continuously uses
the processor shared bus, and (2) it guarantees fairness so as not to
starve one of the processors. Multiprocessor systems that use a
common processor bus should have an arbitration mechanism to avoid
bus contention.  In conventional arbitration methods, a processor
should always perform arbitration before starting to use the
processor bus.  Using this invention, however, the arbitration
overhead can be reduced while keeping the bus use fair to both the
processors.

      Three new signals: HOLD, HLDA, and BREQ, are provided for the
communication between the processors, as shown in Fig. 1. HLDA and
BREQ are abbreviations of HoLD-Acknowledge and Bus-REQuest,
respectively.  HOLD is driven by Processor 2.  HLDA and BREQ are
driven by Processor 1.  When the system is reset, all of the signals
are reset to "0" (inactive).  Assume that each processor controls the
address, data, and command signals on the processor shared bus.  The
processor that has the right to use the bus can arbitrarily drive the
bus signals.  The processor that does not have the right to use the
bus should keep the bus signals in tri-state.

      At the initial state after the system reset, Processor 1 has
the right to use the processor shared bus.  As long as HOLD is
inactive, Processor 1 is allowed to use the bus.  Bus arbitration is
performed as follows.  When Processor 2 needs to use the bus, it
activates HOLD to notify Processor 1 of a bus request.  If Processor
1 recognizes that HOLD is active, it releases the bus an...