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Self Starting Timing Ring Circuit

IP.com Disclosure Number: IPCOM000110123D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 105K

Publishing Venue

IBM

Related People

Widmer, AX: AUTHOR

Abstract

The circuit derives precise cyclic timing tags from a pair of non-overlapping clocks with a resolution equal to the spacing between a rising transition of the first and the second clock, and a stepping rate of twice the rate of the individual input clocks. The cycle time in the example is 10 basic intervals, but any even number 4 or higher can be chosen. The circuit can operate with good margins at high speed and is economical in gate count and power consumption. No Set or Reset inputs are required because the circuit recovers automatically within a few clock cycles from any erroneous state. CIRCUIT DESCRIPTION

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Self Starting Timing Ring Circuit

       The circuit derives precise cyclic timing tags from a
pair of non-overlapping clocks with a resolution equal to the spacing
between a rising transition of the first and the second clock, and a
stepping rate of twice the rate of the individual input clocks.  The
cycle time in the example is 10 basic intervals, but any even number
4 or higher can be chosen.  The circuit can operate with good margins
at high speed and is economical in gate count and power consumption.
No Set or Reset inputs are required because the circuit recovers
automatically within a few clock cycles from any erroneous state.
CIRCUIT DESCRIPTION

      The timing circuit of Fig. 1 is structured as a sequence of
latches, preferably of the polarity hold type, in an open ring
arrangement.  Gates 20, 21, and 22 of Fig. 1 show such a latch; for
all latches but the one shown in detail (7), gate 23 is replaced by
an inverter 22 to provide a complement output. The circuits 20 and 21
represent each a 2 by 1 AND OR INVERT gate. All even numbered latches
0, 2, 4, 6, and 8 at the bottom are clocked by clock +CB0; all
odd numbered latches 1, 3, 5, 7, and 9 at the top are clocked by
clock +CB1.  Typical waveforms for the circuit are illustrated in
Fig. 2.  The clocks +CB0 and +CB1 have no or a limited amount of
overlap at the up level.  A latch implementation with a true and a
complement data input is chosen to eliminate an inversion and the
associated delay in the latch.  For applications at less than
extremely fast clocking rates, a standard latch with just the true
data input may be substituted; there is then no need for a feedback
path from the true output of latch 1 and 9 to the complement data
input of latch 0 and 8, respectively.

      When all the first 8 lat...