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Browse Prior Art Database

Shift Left Arithmetic Overflow Detection

IP.com Disclosure Number: IPCOM000110132D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 3 page(s) / 85K

Publishing Venue

IBM

Related People

Caccamo, PP: AUTHOR [+2]

Abstract

Disclosed is a system that detects overflow when executing fixed point shift left arithmetic instructions. The instruction to cause overflow can be a shift left arithmetic or a shift left double arithmetic. An overflow exists when on the left shift a bit unlike the sign bit is shifted out of bit position 1, or there exists no overflow when the loading number of zeros in an operand minus 1 is equal or greater than the shift amount. For negative operands to find the leading number of ones, the operand is 1's complemented and then treated like a positive operand.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Shift Left Arithmetic Overflow Detection

       Disclosed is a system that detects overflow when
executing fixed point shift left arithmetic instructions.  The
instruction to cause overflow can be a shift left arithmetic or a
shift left double arithmetic.  An overflow exists when on the left
shift a bit unlike the sign bit is shifted out of bit position 1, or
there exists no overflow when the loading number of zeros in an
operand minus 1 is equal or greater than the shift amount.  For
negative operands to find the leading number of ones, the operand is
1's complemented and then treated like a positive operand.

      Positive operands of the shift left arithmetic instruction are
sent to the leading zero bit minus 2 detection mechanism.  The LZB_
MINUS2$(0:5) is the result bus of the LZB-2 detection logic  and can
have a count up to 61 when executing shift left double arithmetic
instructions.  The LZB_MINUS2$ bus is 1's complemented, which is
equivalent to LZB-1, with 2 high order bits '11'B added for line-up
and carry propagation, and added to the SFT_OXF(0:7) field to produce
a sum.  The SFT-OXF(0:7) field contains the shift amount.  (2:7) is
the shift amount, and 0:1 indicate an arithmetic left single or
double.

      Subtracting the leading zero bits minus 1 from the shift amount
of the shift instruction results in an overflow condition:

      IF the sum of the 8-bit adder is all zeros and some special
conditions exist.
      OR

      If the sum of the 8-bit adder is not all zeros but sum (0)=0
and some special conditions exist, as can be seen in the figure and
the following examples.
      Example (1):   Operand  =  LZB_BUS$ to be shifted
                               (See the figure)    000001xx
      Instruction    SLA       (shift left arithmetic single)
      SFT_MOP(0:3)   =    'B'X all arithmetic shifts
      SFT_OXF(0:1)   =    '00'B indicates last cycle of SLA &
                           SLDA
      SFT_OXF(2:7)   =    '000100'B 4 shift amount
      LZB_MINUS2$(0:5)    '000011'B (5-2-3)  $ = signal
      SFT_OXF(0:7)                   00 00 01 00
'11'  1's compl LZB_MINUS2$(0:5)    11 11 11 00
                         C          00 00 00 00   No overflow
                         SUM$(0)
SFT_SCPA_SUM$(0:7) = 0             (output of 8 bit adder)

      When addi...