Browse Prior Art Database

Cache Enabled Memory Test

IP.com Disclosure Number: IPCOM000110140D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 51K

Publishing Venue

IBM

Related People

Barrera, DD: AUTHOR [+3]

Abstract

Memory test during initial program load (IPL) is normally done with cache disabled. This is accomplished in order to be able to use a store-load-compare scheme to achieve memory test. Although this test is effective, it is quite slow due to the process of memory access in the absence of cache capability. Both the instructions and the data must be fetched from system memory when the cache is disabled. As a result, the memory controller that controls memory access is not as effective when compared to cache-enabled situations. The present method performs a memory test utilizing an enabled cache, resulting in a processor which is much more efficient in transferring data out of memory due to the lack of necessity for an instruction fetch.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 80% of the total text.

Cache Enabled Memory Test

      Memory test during initial program load (IPL) is normally done
with cache disabled.  This is accomplished in order to be able to use
a store-load-compare scheme to achieve memory test.  Although this
test is effective, it is quite slow due to the process of memory
access in the absence of cache capability.  Both the instructions and
the data must be fetched from system memory when the cache is
disabled.  As a result, the memory controller that controls memory
access is not as effective when compared to cache-enabled situations.
  The present method performs a memory test utilizing an enabled
cache, resulting in a processor which is much more efficient in
transferring data out of memory due to the lack of necessity for an
instruction fetch.  However, a special setup must be accomplished
prior to memory test, since enabling cache otherwise will void the
memory test.
  The special setup is accomplished utilizing a store of any data to
an address space that is not currently resident within the cache.
Additionally, due to the fact that multiple passes are required for a
memory test when the memory space to be tested is greater than the
cache size, cache miss will always occur, since the memory test is
accomplished sequentially on memory locations.  Therefore, after a
first pass has been completed, the second pass involving a second
pattern will always start from the start-testing location where the
first pattern began.  Since the test...