Browse Prior Art Database

Floating Point Imprecise Interrupts in a Super Scalar System

IP.com Disclosure Number: IPCOM000110151D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 47K

Publishing Venue

IBM

Related People

Barreh, JI: AUTHOR [+3]

Abstract

Disclosed is a method for handling floating-point exceptions in super-scalar systems with multiple instruction dispatch.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 81% of the total text.

Floating Point Imprecise Interrupts in a Super Scalar System

      Disclosed is a method for handling floating-point exceptions in
super-scalar systems with multiple instruction dispatch.

      Previous methods of handling floating-point exceptions in
super-scalar systems required single instruction dispatch.  For many
applications, this proved impractical due to excessive run times.
Super-scalar systems generally issue multiple instructions in a
single clock cycle.  Super-scalar systems perform poorly under single
instruction dispatch constraints.

      A floating-point imprecise (FPI) interrupt handles
floatingpoint exceptions without requiring single instruction
dispatch.  The system at hand may be considered to be made up of:  1)
an icache-unit (ICU), 2) a fixed-point unit (FXU), and 3) a
floating-point unit (FPU).  The FPI interrupt is enabled by setting a
FPI enable bit.  When a floating-point exception is detected by the
FPU, the FPU requests a floating-point imprecise interrupt from the
ICU.  If the FPI enable bit is set, then the ICU stops dispatch the
next cycle.  Once the machine has reached a state where an interrupt
can occur, a FPI interrupt is taken by the ICU.  The FPI interrupt is
not precise, execution cannot resume at the point where the
floating-point exception occurred.  Upon taking a floating-point
imprecise interrupt, the FPI enable bit is disabled. This insures
that FPI interrupts do not continue ndefinitely within the FPI
int...