Browse Prior Art Database

A Method to Accept Discontinuous Data from Memory during an Instruction Cache Reload Sequence

IP.com Disclosure Number: IPCOM000110152D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 51K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+3]

Abstract

Disclosed is a method for handling discontinuous data transfers from memory to a processor during an instruction cache reload. This method allows for flexibility in the design of memory subsystems without affecting the reload interface itself.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 73% of the total text.

A Method to Accept Discontinuous Data from Memory during an Instruction Cache Reload Sequence

      Disclosed is a method for handling discontinuous data transfers
from memory to a processor during an instruction cache reload.  This
method allows for flexibility in the design of memory subsystems
without affecting the reload interface itself.

      In a computer system, the latency of memory transfers is
usually different than the cycle time of the system's processors.
The memory access time is the time from when the processor sends the
address to memory to when the memory sends the first stream of data
back to the processor.  Usually, once the first stream of data from
memory comes back, the rest of the data comes in continuous cycles.
Due to the type of memory used (which determines its speed) or the
basic design of the memory subsystem itself, the data might not come
back from memory in continuous cycles.  If a processor is designed to
trigger on the first set of data from memory, it will accept bad data
on the cycles when the memory data is not present after the initial
data.

      The system at hand consists of an instruction cache unit (ICU)
and a data cache unit (DCU).  During instruction cache reloads,
reload data goes from main memory to the DCU over the memory bus and
from the DCU to the ICU over the instruction-reload bus.  The SCU
(storage control unit) sends a signal to the DCU every cycle that it
wants the DCU to transfer data onto the instr...