Browse Prior Art Database

A Method to Allow Instruction Cache Access during a Reload Sequence

IP.com Disclosure Number: IPCOM000110153D
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 46K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+3]

Abstract

Disclosed is a method which allows a processor to access an instruction cache during a reload sequence resulting in improved system performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 82% of the total text.

A Method to Allow Instruction Cache Access during a Reload Sequence

      Disclosed is a method which allows a processor to access an
instruction cache during a reload sequence resulting in improved
system performance.

      A processor usually has to wait until an instruction cache
reload sequence completes before reaccessing data from the cache
itself.  This is the case since the instruction cache is usually
single-ported.  If the first instruction back from the reload is a
branch to a line present in the cache, then the processor has to wait
for the reload to finish before accessing the cache for the next
instruction.

      A cache reload buffer (CRB) equal to the line size of the
instruction cache allows access to the instruction cache during a
reload sequence.  If a branch instruction is encountered during an
instruction cache reload, the processor can immediately access the
cache.  This is possible since the reload data is being loaded
directly into the CRB instead of the cache.  Once the reload is
completed, the line in the CRB is accessible to the processor as an
additional cache congruence class.  A register is set aside which
holds the address of the cache line in the CRB in order to achieve
this additional congruence class.  This register is used in the hit
logic along with the directory contents to see if the cache line
needed is present in either the CRB or the main cache.  The CRB line
is flushed into the instruction cache at the beginnin...